Semiconductor Device With Recessed Source Electrode

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Solution Overview

Problem

Conventional insulated gate semiconductor devices, such as MOSFET and IGBT, suffer from parasitic element activation during abnormal current conditions, leading to latch-up and short circuits due to uncontrolled parasitic bipolar transistor operation, and size reduction increases current density, making it difficult to maintain low on-voltage.

Innovation Solution

A semiconductor device design featuring a first semiconductor region of one conductivity type and a second semiconductor region with higher impurity concentration, a trench penetrating the second region, and a recessed portion for the source electrode, which prevents parasitic element formation by ensuring the source electrode is embedded deeper than the gate electrode, thereby controlling abnormal current effects and maintaining low on-voltage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If the source electrode is positioned at the surface level to simplify fabrication, then manufacturing precision is improved, but parasitic bipolar transistor activation occurs during abnormal current conditions

Engineering Contradiction:
Improvesource electrode positioningVSAvoidparasitic element suppression
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The source electrode is positioned to extend below the gate electrode in advance, creating a preliminary geometric configuration that prevents parasitic bipolar transistor activation. This pre-positioning ensures that even during abnormal current conditions, the parasitic element cannot form a complete conduction path, thus preventing latch-up before it can occur.

Inventive Principle:
Principle #9Preliminary anti-action

Solution Approach 2:

The solution moves the source electrode positioning from a two-dimensional surface level to a three-dimensional configuration that extends vertically below the gate electrode. This dimensional change in electrode placement creates a geometric relationship that inherently suppresses parasitic element operation while maintaining fabrication feasibility.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If the device size is reduced to improve integration density, then productivity is improved, but current density increases causing higher on-voltage

Engineering Contradiction:
Improveintegration densityVSAvoidon-voltage
Core Design Contradiction:
ProductivityVSLoss of energy

Solution Approach 1:

The source electrode is designed with non-uniform distribution, concentrating conductive material in the critical region below the gate electrode. This local quality enhancement creates a low-resistance path exactly where needed for current flow, reducing on-voltage in the high-current-density regions without increasing overall device size.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The source electrode configuration pre-establishes optimal current distribution paths before the device operates. By positioning the source electrode to extend below the gate electrode, the current is guided through low-resistance regions from the beginning, preventing excessive voltage drop even when device size is reduced for higher integration density.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If the source electrode extends below the gate electrode to suppress parasitic elements, then reliability is improved, but device complexity increases

Engineering Contradiction:
Improveparasitic element suppressionVSAvoidelectrode configuration
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The source electrode configuration merges the source function with the parasitic suppression function into a single integrated structure. By extending the source electrode below the gate electrode, the same geometric feature simultaneously provides electrical connection and prevents parasitic bipolar transistor activation, eliminating the need for separate suppression structures.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS8691635B2Fabrication method of semiconductor device
Publication Date: 2014.04.08 FUJI ELECTRIC CO LTD
  • US8691635B2 patent drawing
  • US8691635B2 patent drawing
  • US8691635B2 patent drawing

AI summary

A semiconductor device includes a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type, disposed on a surface of the first semiconductor region, and having an impurity concentration higher than that of the first semiconductor region; a trench that penetrates the second semiconductor region to reach the first semiconductor region; a first electrode disposed inside the trench via an insulating film; a first recess portion disposed deeper than an upper end of the first electrode, in a surface layer of the second semiconductor region, so as to be in contact with the trench; and a second electrode embedded in the first recess portion.