Semiconductor Device Recessed Wiring Layers
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Solution Overview
Problem
The high cost and inflexibility of semiconductor device manufacturing due to the need for expensive molds and flat metal leads, which restricts the arrangement and miniaturization of elements within the device.
Innovation Solution
A semiconductor device design featuring a semiconductor substrate with a recessed portion, multiple wiring layers, and an insulating film that allows for three-dimensional arrangement of circuit elements, eliminating the need for external leads and enabling cost-effective production and size reduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional punching process with mold is used to form leads, then leads can be formed efficiently and accurately, but the cost increases significantly when function or shape changes require remaking molds
Solution Approach 1:
The patent transitions from traditional flat metal leads to three-dimensional wiring structures formed directly on the semiconductor substrate. Multiple wiring layers are stacked vertically, allowing complex electrical connections to be achieved within the substrate plane rather than requiring external flat leads, thereby eliminating mold dependency for lead formation
Solution Approach 2:
The invention extracts and eliminates the separate lead component from the traditional semiconductor device structure. Instead of using external metal leads formed by punching, the electrical connection function is integrated directly into the substrate through formed wiring layers, removing the need for expensive molds used in lead formation
2Ease of operation
If flat metal leads are used to connect elements, then elements can be supported and connected, but the arrangement of multiple elements is restricted and device size cannot be reduced
Solution Approach 1:
The patent employs multiple wiring layers stacked in the vertical dimension to achieve three-dimensional element arrangement. This allows elements to be positioned at different heights (Z-axis) while maintaining electrical connections through the layered wiring structure, thereby reducing the planar footprint and overall device size
Solution Approach 2:
The invention implements nested wiring structures where multiple wiring layers are stacked vertically within the substrate. Inner wiring layers are surrounded and connected by outer layers, creating a compact three-dimensional network that supports complex element arrangements in limited space
3Ease of manufacture
If elements are arranged in flat configuration, then manufacturing is simpler, but higher mounting accuracy and three-dimensional arrangement cannot be achieved
Solution Approach 1:
The patent forms wiring structures in three dimensions using multiple stacked layers within the substrate, enabling precise positioning of elements at different vertical levels. This three-dimensional wiring approach provides higher mounting accuracy by allowing elements to be positioned optimally in space rather than constrained to a flat plane
Data Source
AI summary
A semiconductor device includes a semiconductor substrate, a conducting portion, and a sealing resin. The substrate has a main surface and is formed with a recessed portion in the main surface. The conducting portion is formed on the substrate. The sealing resin is disposed in the recessed portion. The conducting portion includes a first wiring layer and a second wiring layer both formed in the recessed portion. The second wiring layer is closer to the main surface than is the first wiring layer in the normal direction of the main surface.