Semiconductor Redistribution Pads Grid Arrangement
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving high signal transferring speed and reduced pattern size while maintaining improved electrical characteristics, which is essential for high-performance and high-density semiconductor devices.
Innovation Solution
The semiconductor device incorporates a redistribution structure with specifically arranged redistribution pads, including at least two rows of input/output pads and power/ground pads, to reduce the size and enhance electrical characteristics by optimizing the arrangement and length of the redistribution structure between electric and redistribution pads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the redistribution structure length is reduced to improve electrical characteristics, then signal transferring speed and electrical characteristics are improved, but the arrangement flexibility of pads is reduced
Solution Approach 1:
The patent transitions from traditional linear pad arrangements to a two-dimensional grid pattern where input/output pads and power/ground pads are arranged in intersecting rows and columns. This dimensional change allows pads to be positioned at multiple locations across the substrate, reducing redistribution structure lengths while maintaining arrangement flexibility through the grid's geometric constraints.
Solution Approach 2:
The pad structure is segmented into distinct functional groups: input/output pads arranged in first and second rows, and power/ground pads arranged in third and fourth rows. This segmentation allows independent optimization of each pad type's position and connection path, enabling reduced redistribution lengths for signal pads while separately optimizing power delivery paths.
2Area of stationary object
If pads are arranged to reduce semiconductor device size, then device footprint is reduced, but electrical characteristics may deteriorate due to longer redistribution structures
Solution Approach 1:
By arranging pads in a two-dimensional grid pattern with input/output pads in horizontal rows and power/ground pads in vertical rows, the invention maximizes spatial utilization of the substrate. This allows compact device footprint while keeping redistribution paths short through optimal geometric positioning at grid intersections.
Solution Approach 2:
The patent applies different arrangement strategies to different pad types: input/output pads are arranged in dedicated signal rows with corresponding column intersections, while power/ground pads are arranged in separate power rows. This local optimization ensures each pad type achieves its specific electrical performance requirements within the compact overall layout.
3Area of stationary object
If power/ground pads are placed between input/output pad rows, then device size is reduced and power supply efficiency is improved, but noise interference between signal and power paths may increase
Solution Approach 1:
The patent segments power/ground pads into separate dedicated rows (third and fourth rows) distinct from input/output pad rows (first and second rows). This segmentation creates clear spatial separation between signal paths and power paths, reducing electromagnetic coupling and noise interference while achieving compact integration through the grid arrangement.
Solution Approach 2:
By providing separate ground pads in the fourth row corresponding to power pads in the third row, the invention creates localized equipotential regions for power delivery. This reduces ground bounce and voltage fluctuations that could couple into adjacent signal paths, minimizing noise interference in the compact layout.
Data Source
AI summary
Semiconductor devices with redistribution pads are disclosed. The semiconductor device includes a plurality of electric pads provided on a semiconductor substrate, and a plurality of redistribution pads electrically connected to the electric pads and an outer terminal. The plurality of redistribution pads includes a plurality of first redistribution pads constituting a transmission path for a first electrical signal and at least one second redistribution pad constituting a transmission path for a second electrical signal different from the first electrical signal. The first redistribution pads are arranged on the semiconductor substrate to form at least two rows, and the at least one second redistribution pad is disposed between the at least two rows of the first redistribution pads.