Semiconductor Redistribution Pattern for Power Delivery
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Solution Overview
Problem
Semiconductor devices face challenges in power delivery due to insufficiency, particularly during scaling down, leading to performance and reliability issues.
Innovation Solution
The semiconductor device design includes an edge power via and assisted via to alleviate power delivery insufficiency, with a redistribution power pattern electrically coupled to the center and edge power pads, improving power distribution and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor devices are scaled down to meet increasing computing demand, then device density and computing ability are improved, but power delivery insufficiency and reliability issues worsen
Solution Approach 1:
The power delivery network is segmented into multiple independent power paths: a first power path from center power pads through the substrate to center power regions, and a second power path from edge power pads through the substrate to edge power regions. This segmentation allows power to be delivered through distributed routes, reducing the burden on any single path and improving overall reliability during scaling.
Solution Approach 2:
The patent transitions from traditional center-only power delivery to a two-dimensional power distribution architecture by adding edge power pads and center power pads at opposite locations on the substrate. This dimensional expansion creates multiple spatial routes for power delivery, addressing power insufficiency in scaled-down devices through spatial distribution rather than increasing current density in existing paths.
2Area of stationary object
If power delivery paths are extended to reach edge regions, then power distribution coverage is improved, but parasitic inductance and capacitance increase
Solution Approach 1:
The patent implements local power delivery by placing both center power pads and edge power pads directly on the substrate surface at their respective locations. This local quality approach allows power to be delivered close to the power consumption regions without requiring long extended paths through the substrate, thereby reducing parasitic inductance and capacitance while maintaining wide power distribution coverage.
Data Source
AI summary
The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first substrate including a center region and an edge region distal from the center region, a first circuit layer positioned on the first substrate, a center power pad positioned in the first circuit layer and above the center region, an edge power pad positioned in the first circuit layer, above the edge region, and electrically coupled to the center power pad, a redistribution power pattern positioned above the first circuit layer and electrically coupled to the center power pad, and an edge power via positioned between the edge power pad and the redistribution power pattern, and electrically connecting the edge power pad and the redistribution power pattern. The first substrate, the center power pad, the edge power pad, the redistribution power pattern, and the edge power via together configure a first semiconductor die.