Semiconductor Reliability Verification Unit for Low-k Material Impact Detection

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Solution Overview

Problem

Semiconductor devices with low dielectric constant materials are prone to damage from physical impacts during fabrication processes, such as sawing and bonding, leading to defects like cracks, peeling, and delamination, which are difficult to detect and verify.

Innovation Solution

A semiconductor device with a reliability verifying unit that includes a chip guard-ring and a reliability-verifying-signal transmitting unit, comprising inverters and NMOS transistors, which generates and delays a reliability verifying signal to detect faults by comparing signal states and periods before and after physical impacts, allowing for the identification of abnormalities.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If low dielectric constant materials are used to increase capacity and speed, then operation frequency and storage capacity are improved, but the semiconductor chip becomes more susceptible to damage from physical impact during fabrication

Engineering Contradiction:

Improveoperation frequencyVSAvoidresistance to physical impact damage

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

The patent implements a reliability verifying unit that performs fault detection before the semiconductor chip is shipped. This preliminary verification action identifies potential defects caused by physical impact during fabrication processes like sawing and bonding, allowing defective chips to be filtered out before reaching the customer, thus resolving the contradiction between using fragile low-k materials and ensuring product reliability

Inventive Principle:

Principle #10Preliminary action

2Ease of manufacture

If physical impact is applied during sawing and bonding processes, then fabrication is completed, but faults such as cracks, peeling, and delamination occur that are difficult to detect

Engineering Contradiction:

Improvefabrication process completionVSAvoidfault detection difficulty

Core Design Contradiction:

Ease of manufactureVSDifficulty of detecting and measuring

Solution Approach 1:

The patent introduces a reliability verifying unit as an intermediary detection mechanism between the fabrication process and final product delivery. This unit uses signal transmission through conductors to indirectly detect faults like cracks and delamination that are difficult to observe directly, enabling effective quality control without interfering with the fabrication process

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent replaces direct mechanical inspection methods with electrical signal-based detection. By transmitting test signals through conductors and measuring signal characteristics (period, pulse width), the system can detect mechanical faults like cracks and delamination without requiring physical disassembly or destructive testing, thus solving the detection difficulty

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

3Reliability

If a reliability verifying unit is added to detect faults, then reliability verification capability is improved, but device complexity increases

Engineering Contradiction:

Improvefault detection capabilityVSAvoidcircuit structure complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The reliability verifying unit is designed to perform multiple functions: it can detect various types of faults (cracks, delamination, bonding defects), work with different signal types, and operate during normal chip functionality testing. This multi-functionality justifies the added complexity by providing comprehensive reliability verification across multiple failure modes

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The reliability verifying unit utilizes the chip's own existing structures (conductors, circuit elements) as part of the detection pathway. Rather than requiring entirely separate external testing equipment, the chip's internal structures serve dual purposes: normal operation and reliability verification, thereby reducing the relative complexity burden

Inventive Principle:

Principle #25Self-service

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively reduces the failure rate of semiconductor devices by detecting and preventing faults caused by physical impacts during fabrication, ensuring the reliability of semiconductor chips by identifying changes in signal transmission and periods, thereby enhancing the detection of abnormalities.

Implementation Method 1

the reliability-verifying-signal transmitting unit comprises at least one inverter and at least one electrical conductor connected in series

Methodology Applied

Scientific EffectSignal inversion and transmission delay:

Implementation Method 2

the NMOS transistor applies a signal having a logic low state to the input of the at least one inverter while in an electromigration acceleration mode

Methodology Applied

Scientific EffectElectromigration:

Data Source

PatentUS8362795B2Semiconductor device capable of verifying reliability

Publication Date: 2013.01.29 SAMSUNG ELECTRONICS CO LTD

AI summary

A semiconductor device includes an integrated semiconductor circuit unit, a chip guard-ring disposed along an outer portion of the semiconductor device, and a reliability verifying unit disposed between the integrated semiconductor circuit unit and the chip guard-ring. The reliability verifying unit is configured to delay a reliability verifying signal to detect a fault while in a reliability detecting mode.