Semiconductor Device Resin Sealing and Post Electrode Piercing

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Solution Overview

Problem

The challenge in reducing the thickness of semiconductor devices using flip-chip bonding techniques is compounded by difficulties in handling thin semiconductor chips and the Au-Au pressure bonding process, which leads to underfill material adherence and potential damage to the side surfaces of the first semiconductor chip.

Innovation Solution

A semiconductor device structure featuring a first semiconductor chip with a second semiconductor chip flip-chip bonded to it, sealed by a resin portion that exposes the lower surface of the first chip and upper surface of the second chip, while covering the side surface of the first chip, and a post electrode that pierces the resin portion for connection, along with a manufacturing method involving post electrode formation, groove creation, resin sealing, grinding, and polishing to reduce thickness and prevent damage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of stationary object

If the second semiconductor chip is made thinner to reduce device thickness, then the packaging density is improved, but the handling difficulty increases and the chip is more prone to damage

Engineering Contradiction:
Improvethickness of semiconductor deviceVSAvoidhandling of semiconductor chip
Core Design Contradiction:
Length of stationary objectVSEase of operation

Solution Approach 1:

The patent applies beforehand cushioning by forming a resin portion that covers the side surface of the first semiconductor chip before the flip-chip bonding process. This resin portion acts as a protective cushion during handling and bonding operations, preventing damage to the thin second semiconductor chip while enabling reduced device thickness

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

2Strength

If the Au-Au pressure bonding process is used for flip-chip bonding, then the bonding strength is improved, but the underfill material adheres to the bonding tool and the thin chip causes processing difficulties

Engineering Contradiction:
Improvebonding strengthVSAvoidmanufacturing process difficulty
Core Design Contradiction:
StrengthVSEase of manufacture

Solution Approach 1:

The patent introduces an intermediary resin portion that covers the side surface of the first semiconductor chip during the Au-Au pressure bonding process. This resin portion serves as a mediator that prevents underfill material from adhering to the bonding tool while allowing the pressure bonding process to proceed effectively, thus maintaining bonding strength while easing manufacturing difficulties

Inventive Principle:
Principle #24Intermediary (Mediator)

3Device complexity

If the side surface of the first semiconductor chip is exposed, then the chip structure is simplified, but the chip is vulnerable to damage during testing and packaging

Engineering Contradiction:
Improvechip structureVSAvoidchip damage resistance
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent applies beforehand cushioning by forming a resin portion that covers the side surface of the first semiconductor chip. This resin portion provides protective cushioning during subsequent testing and packaging operations, preventing damage to the chip while maintaining a relatively simple overall structure

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Data Source

PatentUS8492890B2Semiconductor device and method for manufacturing thereof
Publication Date: 2013.07.23 CYPRESS SEMICONDUCTOR CORP
  • US8492890B2 patent drawing
  • US8492890B2 patent drawing
  • US8492890B2 patent drawing

AI summary

A semiconductor device which includes a first semiconductor chip, a second semiconductor chip flip-chip bonded to the first semiconductor chip, a resin portion for sealing the first semiconductor chip and the second semiconductor chip such that a lower surface of the first semiconductor chip and an upper surface of the second semiconductor chip are exposed and a side surface of the first semiconductor chip is covered, and a post electrode which pierces the resin portion and is connected to the first semiconductor chip, and a manufacturing method thereof are provided.