Semiconductor Retention Circuit Power Isolation
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Solution Overview
Problem
Integrated circuits face challenges in reducing power consumption during sleep mode without losing data, as existing solutions often require retention circuits within the logic circuit area, leading to increased current consumption and inefficient design.
Innovation Solution
A semiconductor device with separate unit regions for logic and retention circuits, where the retention circuits receive second power and store data during sleep mode, allowing the logic circuits to be electrically separated and reducing power consumption by blocking first power during sleep.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If retention circuits are integrated within the logic circuit area, then data retention during sleep mode is achieved, but current consumption increases and design efficiency decreases
Solution Approach 1:
The patent divides the circuit into separate logic circuit regions and retention circuit regions. Retention circuits are extracted from the logic circuit area and placed in dedicated retention regions, allowing independent power management. This segmentation enables the logic circuits to be completely powered down during sleep mode while retention circuits maintain data using separate power supply lines.
Solution Approach 2:
The patent extracts retention circuits from the logic circuit area and places them in separate retention circuit regions. This extraction removes the source of unnecessary current consumption from the logic circuit area, allowing logic circuits to be fully powered down while retention circuits continue operating with dedicated power supply to maintain data.
2Use of energy by moving object
If logic circuits are powered down during sleep mode, then power consumption is reduced, but data is lost without retention circuits
Solution Approach 1:
The patent introduces separate power supply lines as intermediaries between the power source and retention circuits. These dedicated power lines allow retention circuits to receive power independently from logic circuits, enabling selective power management where logic circuits are powered down but retention circuits continue operating to preserve data.
Solution Approach 2:
The patent segments the power supply system into separate power lines for logic circuits and retention circuits. This segmentation allows independent control of power delivery, enabling logic circuits to be powered down during sleep mode while retention circuits maintain their own power supply to preserve data without loss.
3Ease of manufacture
If retention circuits are placed in separate regions, then design efficiency improves and power management becomes easier, but circuit complexity increases
Solution Approach 1:
The patent creates retention circuit regions that serve multiple functions: data retention during sleep mode, scan chain operations for testing, and configurable connectivity through multiplexers. This multi-functionality reduces the need for separate dedicated circuits for each function, thereby reducing overall circuit complexity despite the spatial separation.
Solution Approach 2:
The patent introduces dynamic connectivity control through multiplexers that can switch between connecting retention circuits to logic circuits or to scan chains. This dynamic reconfiguration capability allows the same retention circuit infrastructure to serve different purposes based on operational mode, reducing the need for separate static circuits and thereby reducing overall complexity.
Data Source
AI summary
A semiconductor device includes first power lines through which first power is supplied, a plurality of unit regions defined by the first power lines, and second power lines through which second power is supplied. Each of the unit regions includes a logic circuit suitable for operating by receiving the first power from at least one of the first power lines during a normal mode, and a retention circuit suitable for operating by receiving the second power from at least one of the second power lines, receiving data from the logic circuit when an operation mode changes from the normal mode to a sleep mode, and keeping the data during the sleep mode. The logic circuit is electrically separated from the second power lines.