Semiconductor Ring Structure for Layer Flatness Control
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Solution Overview
Problem
The semiconductor industry faces challenges in controlling the flatness of underlying layers during lithography operations, particularly in the integration of non-volatile memory cells and peripheral logic circuits, as manufacturing processes become increasingly complex with the scaling down of flash memory in advanced CMOS logic integrated circuits.
Innovation Solution
A semiconductor device is manufactured with a ring structure made of active regions surrounding non-volatile memory cell and logic circuit areas, utilizing a stacked structure with polysilicon layers and high-k dielectric films to form isolation and gate structures, which includes a substrate etching process and multiple layer formations to ensure precise control and separation between memory and logic areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If non-volatile memory cells and peripheral logic circuits are integrated in advanced CMOS processes, then device density and performance are improved, but manufacturing process complexity increases
Solution Approach 1:
The patent divides the semiconductor device into distinct memory cell areas and peripheral logic circuit areas, with separate manufacturing processes for each region. This segmentation allows different process optimizations for memory and logic portions, reducing overall manufacturing complexity while maintaining high device density through integrated fabrication.
2Productivity
If flash memory is scaled down to nanometer technology nodes, then device density is improved, but control of underlying layer flatness during lithography deteriorates
Solution Approach 1:
The patent implements region-specific structures including memory isolation structures in the memory cell area and separate isolation structures in the peripheral logic area. These localized structural modifications address flatness control issues in specific regions without affecting the entire device, enabling continued scaling to nanometer nodes while maintaining lithography precision.
3Adaptability or versatility
If multiple manufacturing processes are integrated for memory and logic circuits, then device functionality is improved, but process control difficulty increases
Solution Approach 1:
The patent employs preliminary process steps including forming pad oxide layers and nitride layers before subsequent processing, and uses preliminary isolation structure formation to prepare the substrate for different memory and logic processes. These advance preparations establish a controlled foundation that facilitates precise process control throughout the integrated manufacturing sequence.
Data Source
AI summary
In a method of manufacturing a semiconductor device, the semiconductor device includes a non-volatile memory formed in a memory cell area and a ring structure area surrounding the memory cell area. In the method, a protrusion of a substrate is formed in the ring structure area. The protrusion protrudes from an isolation insulating layer. A high-k dielectric film is formed, thereby covering the protrusion and the isolation insulating layer. A poly silicon film is formed over the high-k dielectric film. The poly silicon film and the high-k dielectric film are patterned. Insulating layers are formed over the patterned poly silicon film and high-k dielectric film, thereby sealing the patterned high-k dielectric film.