Semiconductor Scan Test FIFO Asynchronous Clock Domain Crossing
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Solution Overview
Problem
Existing scan test methods face challenges in performing timing violations and increased test time due to asynchronous clock signals in semiconductor devices, particularly in regions with dynamic voltage and frequency scaling, where static timing analysis is complex, and traditional solutions either fail to prevent setup time violations or require loading all data before starting the test.
Innovation Solution
A semiconductor device with a FIFO (First In First Out) storage system that operates asynchronously with different clock signals, allowing for simultaneous data accumulation and test execution across regions with varying voltages, using a test pattern generation device, test control device, and test result compression device to manage scan test data and results efficiently, thereby reducing timing violations and test duration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If test data is supplied to multiple scan chains in synchronization with a clock at a constant rate, then correct test data can be supplied to all flip-flops, but timing violations occur when clocks in different regions are asynchronous
Solution Approach 1:
The patent introduces a FIFO (First-In-First-Out) buffer as an intermediary between the CONST region and DVFS region. The FIFO decouples the asynchronous clock domains, allowing test data to be written at one clock rate and read at another clock rate without causing timing violations. This mediator absorbs the clock frequency differences and enables reliable data transfer across the boundary.
Solution Approach 2:
The patent changes the clock frequency parameter by using different clock rates for writing to and reading from the FIFO. The write clock can operate at a higher frequency while the read clock operates at a lower frequency, allowing the system to adapt to the asynchronous nature of the clock domains and avoid setup and hold time violations.
2Manufacturing precision
If the processing rate of the circuit is reduced to allow sufficient timing margin, then timing violations are avoided, but runtime test execution time requirement cannot be satisfied
Solution Approach 1:
The patent applies dynamic voltage and frequency scaling (DVFS) to the scan chain in the DVFS region, allowing the clock frequency to be dynamically adjusted. During normal operation, the scan chain can run at a higher frequency to meet test execution time requirements, while during test mode, the frequency can be adjusted to ensure proper timing margins. This dynamic adjustment resolves the contradiction between speed and timing reliability.
3Manufacturing precision
If scan-in data is accumulated in a FIFO in synchronization with a low-rate scan clock, then hold-time violations are avoided, but setup time violations cannot be avoided and test time increases
Solution Approach 1:
The patent performs preliminary action by pre-loading test data into the FIFO during idle periods or low-utilization times. This allows the scan chain to quickly access pre-prepared test patterns during actual testing, reducing the overall test execution time while still maintaining proper timing margins through the FIFO's buffering capability.
4Adaptability or versatility
If a CPU core is located in a DVFS region and a runtime test control circuit is located in a CONST region, then dynamic voltage and frequency scaling is enabled, but static timing analysis becomes virtually impossible
Solution Approach 1:
The patent segments the device into distinct clock domains: a CONST region with stable clock signals for the test control circuit, and a DVFS region with dynamically scalable clock signals for the CPU core. By segmenting the design and using a FIFO at the boundary, the patent enables independent timing analysis for each region, making static timing analysis feasible despite the presence of DVFS.
Data Source
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AI summary
A semiconductor device (9) according to the present invention includes a FIFO (91), a test data write circuit (92) that sequentially writes a plurality of test data to the FIFO (91) in synchronization with a first clock signal (910), and a test control circuit (93) that, in parallel with writing of the plurality of test data to the FIFO (91) by the test data write circuit (92), sequentially reads a plurality of test data stored in the FIFO (91) in synchronization with a second clock signal (920) that is not synchronous with the first clock signal (910) and performs a scan test of a circuit to be tested (94).