Semiconductor Scan-Layer Control for Reliable, Low-Power Testing
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Solution Overview
Problem
Existing semiconductor integrated circuit testing methods face challenges in efficiently and reliably detecting failures, particularly in scan flip-flops and combinational circuits, while minimizing power consumption and test time.
Innovation Solution
The semiconductor integrated circuit is configured with multiple scan layers and a test control circuit that allows independent testing of each layer, setting non-selected layers to a waiting state during data holding periods, and using decompression/compression circuits to reduce scan flip-flop count, enabling simultaneous testing across multiple circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple scan layers are tested simultaneously using traditional methods, then test time is reduced, but test reliability deteriorates due to inability to detect failures in scan flip-flops and combinational circuits
Solution Approach 1:
The core circuit is divided into multiple scan layers (first scan layer, second scan layer, etc.), each with independent scan chains and combinational circuits. This segmentation allows the test system to focus on one layer at a time, ensuring reliable failure detection while maintaining overall test efficiency through structured organization of the circuit under test.
Solution Approach 2:
Before testing each scan layer, the test control circuit performs preliminary actions by setting non-selected scan layers to a waiting state and preparing the selected layer with test data and clock signals. This preliminary preparation ensures that when a layer is actively tested, all necessary conditions are already in place, enabling reliable detection without interfering with other layers.
2Reliability
If all scan layers are actively tested at the same time, then test coverage is improved, but power consumption increases
Solution Approach 1:
The test system employs periodic action by cyclically selecting different scan layers for active testing while placing others in waiting state. Each layer undergoes comprehensive testing during its selected period, ensuring full coverage across all layers over time, while power consumption is managed by keeping non-selected layers inactive rather than continuously active.
Solution Approach 2:
By segmenting the core circuit into multiple independent scan layers with separate control, the system can activate only the necessary layer during each test cycle. This segmentation enables selective power management where only the currently tested layer consumes significant power, while other layers remain in low-power waiting states, thus reducing overall power consumption while maintaining comprehensive test coverage.
3Reliability
If scan chains are extended to cover more flip-flops, then test coverage is improved, but test time increases
Solution Approach 1:
The scan chains are segmented into multiple scan layers, with each layer containing a subset of flip-flops. This segmentation allows the test system to cover all flip-flops across all layers through sequential testing of each layer, rather than requiring one extremely long scan chain. The total test time is managed by efficiently cycling through layers, achieving comprehensive coverage without the time penalty of a single extended scan chain.
Solution Approach 2:
Instead of extending scan chains in one dimension (adding more flip-flops to a single chain), the invention adds another dimension by creating multiple parallel scan layers. Each layer can be tested independently with optimized chain lengths, and the multi-layer structure provides comprehensive coverage by testing different portions of the circuit in different layers, thus achieving full coverage without proportionally increasing test time.
4Ease of manufacture
If decompression/compression circuits are added to reduce scan flip-flop count, then device complexity increases, but manufacturing cost decreases
Solution Approach 1:
The decompression and compression circuits serve multiple functions: they reduce the number of scan flip-flops required, enables multi-layer scan testing, and provide interfaces between the test control circuit and the core circuit. By making these circuits multi-functional, the added complexity is justified by the significant reduction in flip-flop count and the enabling of comprehensive multi-layer testing, ultimately reducing manufacturing cost through more efficient circuit design.
Data Source
AI summary
According to one embodiment, a circuit includes: a core circuit including first and second scan layers; and a test control circuit that controls a scan test on the first and second scan layers. The test control circuit supplies a first test data and a first shift clock to the first scan layer and then sets the first scan layer to a waiting state, supplies a second test data and a second shift clock to the second scan layer during a period in which the first scan layer is in the waiting state, sets the second scan layer to a waiting state after supplying the second test data and the second shift clock to the second scan layer, and supplies a first launch clock and a first capture clock to the first scan layer after setting the second scan layer to the waiting state.