Semiconductor Contact Trench Sealing Layer for Low Resistance
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Solution Overview
Problem
As semiconductor devices continue to scale down, there is a need for improved sealing layers to reduce resistance and enhance device performance, particularly in CMOS devices where feature sizes are decreasing, leading to increased power dissipation and manufacturing complexity.
Innovation Solution
A self-aligned, well-ordered monolayer sealing layer is formed using Si-containing precursors that chemisorb to the hydroxyl groups on the sidewalls of contact trenches, preventing diffusion and improving adhesion, which is deposited using thermal CVD or ALD processes, and optionally accompanied by a barrier layer to further prevent metal diffusion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes are decreased to increase functional density, then production efficiency is improved and costs are lowered, but power dissipation increases and device performance deteriorates
Solution Approach 1:
The patent changes the material parameters of the sealing layer by using silicon-containing precursors that chemisorb to hydroxyl groups, forming a monolayer with specific electrical properties. This parameter change in the sealing layer material composition helps reduce contact resistance and mitigate power dissipation effects in scaled-down devices
Solution Approach 2:
The sealing layer acts as an intermediary between the conductive feature and the dielectric layer, preventing direct contact and unwanted diffusion while maintaining electrical connectivity. This intermediary layer reduces contact resistance and improves power efficiency in miniaturized devices
2Ease of manufacture
If conventional sealing layers are used in scaled-down devices, then manufacturing complexity is reduced, but contact resistance increases and device performance deteriorates
Solution Approach 1:
The sealing layer formation process is self-aligned, where silicon-containing precursors automatically chemisorb to hydroxyl groups on the sidewalls of contact trenches. This self-service mechanism eliminates the need for additional alignment steps and complex manufacturing processes while ensuring low contact resistance
Solution Approach 2:
The patent replaces mechanical deposition methods with a chemical self-assembly process where precursors chemisorb to form the sealing layer. This substitution of mechanical systems with chemical processes simplifies manufacturing while achieving superior electrical contact properties
3Device complexity
If no sealing layer is formed, then manufacturing complexity is minimized, but material diffusion occurs and device reliability deteriorates
Solution Approach 1:
The patent extracts only the essential sealing function by forming a minimal monolayer structure that prevents material diffusion without requiring complex multi-layer sealing structures. This extracted essential function maintains reliability while minimizing device complexity
Solution Approach 2:
The sealing layer is formed as a thin monolayer film that provides sufficient diffusion barrier properties without the complexity of thick or multi-layer structures. This thin film approach prevents material diffusion while keeping the device structure simple
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The self-aligned sealing layer reduces contact resistance and improves device performance by preventing material diffusion and reactions, while the barrier layer ensures additional adhesion and conductivity, thus enhancing the integration and efficiency of semiconductor structures.
Implementation Method 1
Si-containing precursors that chemisorb to the hydroxyl groups on the sidewalls of contact trenches
Implementation Method 2
deposited using thermal CVD or ALD processes
Implementation Method 3
deposited using thermal CVD or ALD processes
Data Source
AI summary
The present disclosure provides a method for forming a semiconductor structure. In accordance with some embodiments, the method includes providing a substrate and a conductive feature formed over the substrate; forming a low-k dielectric layer over the conductive feature; forming a contact trench aligned with the conductive feature; and selectively growing a sealing layer which is a monolayer formed on sidewalls of the contact trench.