Semiconductor Selector Pattern via Radical Oxidation

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Solution Overview

Problem

Existing semiconductor devices face challenges in forming selector patterns with high-density oxide layers to prevent micro voids and ensure reliable electrical connections, leading to compromised performance due to low-density oxide layers formed by deposition processes.

Innovation Solution

The formation of high-density oxide layers through a radical oxidation process, followed by ion implantation to incorporate dopants, which enhances the density and reduces vacancies, thereby improving the interface and electrical connection between the selector pattern and the lower electrode pattern.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a deposition process using source gases including Si and O2 is used to form the oxide layer, then the manufacturing process is simple, but the oxide layer has low density and contains micro voids

Engineering Contradiction:
Improveoxide layer densityVSAvoidprocess complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent changes the formation method of the oxide layer from a deposition process to a radical oxidation process. This parameter change transforms the oxide layer formation mechanism, enabling high-density oxide layers without micro voids while maintaining process feasibility through controlled oxidation conditions

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent replaces the physical deposition mechanism with a chemical oxidation mechanism. Instead of depositing oxide material from source gases, the process uses radical oxidation to convert silicon-containing material into high-density oxide in-situ, eliminating the formation of micro voids associated with deposition

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Reliability

If a deposition process is used to form the oxide layer, then the process is easier to manufacture, but micro voids are formed reducing electrical connection reliability

Engineering Contradiction:
Improveelectrical connection reliabilityVSAvoidmanufacturing ease
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent modifies the oxide layer formation parameter from deposition to radical oxidation, which fundamentally changes the material structure to eliminate micro voids. This ensures reliable electrical connections while the process remains manufacturable through controlled oxidation conditions

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent performs preliminary oxidation of the silicon-containing layer before subsequent processing steps. By converting the silicon layer to high-density oxide in advance, the process prevents micro void formation that would otherwise compromise electrical connection reliability in later manufacturing stages

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach results in improved Time Dependent Dielectric Breakdown (TDDB) characteristics and prevents the formation of micro voids, leading to enhanced reliability and performance of the semiconductor memory cells.

Implementation Method 1

performing a radical oxidation process to covert a first portion of the initial Si-containing layer into an oxide layer including silicon dioxide (SiO2)

Methodology Applied
Scientific EffectRadical oxidation: Oxidation

Implementation Method 2

incorporating a dopant into the oxide layer by an ion implantation process to form a selector pattern

Methodology Applied
Scientific EffectIon implantation: Ion Implantation

Data Source

PatentUS20230142183A1Semiconductor device and method for fabricating the same
Publication Date: 2023.05.11 SK HYNIX INC
  • US20230142183A1 patent drawing
  • US20230142183A1 patent drawing
  • US20230142183A1 patent drawing

AI summary

A method for fabricating a semiconductor device including a plurality of memory cells. The method includes: forming a first electrode layer; forming an initial Si-containing layer over the first electrode layer; performing a radical oxidation process to covert a first portion of the initial Si-containing layer into an oxide layer including silicon dioxide (SiO2) and form a Si-containing layer under the oxide layer by using a second portion of the initial Si-containing layer; and incorporating a dopant into the oxide layer by an ion implantation process to form a selector pattern.