Semiconductor Self-Refresh Impedance Control via Segmented Buffers
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Solution Overview
Problem
In semiconductor devices with self-refresh mode, the impedance control signal cannot be used during the self-refresh mode due to inactivation of input first-stage circuits, leading to higher power consumption when entering a power-down mode to utilize ODT function, and existing solutions fail to address this issue effectively.
Innovation Solution
A semiconductor device and controller system that includes an access control circuit capable of issuing an impedance control command during the self-refresh mode, allowing the impedance of data terminals to be controlled through a second input buffer circuit that remains active, bypassing the latch circuit that synchronizes with the clock signal, enabling impedance control asynchronously with the external clock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the semiconductor device enters self-refresh mode to reduce power consumption, then power consumption is reduced, but the impedance control signal cannot be used and the ODT function becomes unavailable
Solution Approach 1:
The patent divides the input buffer circuits into two separate circuits: a first input buffer circuit for receiving clock signals and a second input buffer circuit for receiving impedance control commands. This segmentation allows the second input buffer circuit to remain active during self-refresh mode while the first input buffer circuit can be inactivated, thereby maintaining impedance control capability while reducing power consumption.
Solution Approach 2:
The second input buffer circuit is designed to handle impedance control commands independently of the clock signal path, enabling it to function during self-refresh mode when the clock receiver is inactivated. This multi-functionality ensures that the ODT function remains available even when the device is in low-power self-refresh mode.
2Use of energy by moving object
If the clock receiver is inactivated during self-refresh mode to reduce power consumption, then power consumption is reduced, but the impedance control signal cannot be received synchronously with the clock signal
Solution Approach 1:
The patent separates the clock signal reception function from the impedance control command reception function by using two distinct input buffer circuits. The second input buffer circuit is dedicated to receiving impedance control commands and remains active during self-refresh mode, enabling asynchronous reception of impedance control signals independent of the clock signal status.
3Adaptability or versatility
If the semiconductor device enters power-down mode to use the ODT function, then impedance control is available, but power consumption increases
Solution Approach 1:
The patent divides the input buffer circuits into two separate circuits: a first input buffer circuit to which an external clock signal is supplied and a second input buffer circuit supplied with an impedance control command. This segmentation allows the second input buffer circuit to remain active during self-refresh mode while the first input buffer circuit can be inactivated, enabling impedance control without entering power-down mode.
Solution Approach 2:
The patent enables dynamic operation of the second input buffer circuit, allowing it to remain active during self-refresh mode when the clock receiver is inactivated. This dynamic configuration allows the system to adaptively maintain impedance control capability during low-power modes, eliminating the need to transition to power-down mode solely for ODT function availability.
Data Source
AI summary
A method for controlling termination impedance of a data terminal in a dynamic random access memory device includes receiving a mode register set command to set an operation mode to a first mode, setting the operation mode in a mode register to the first mode, receiving a self-refresh entry command, entering self-refresh mode, activating a first input buffer connected to a termination impedance control terminal, and receiving an impedance control signal at the first buffer, wherein the termination impedance of the data terminal is set to a first impedance value if the termination impedance control signal has a first level and the termination impedance of the data terminal is set to a second impedance value if the termination impedance control signal has a second level.