Semiconductor Device With Segmented Isolation Patterns

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Solution Overview

Problem

Current semiconductor devices face challenges in achieving improved electrical characteristics, particularly in the integration of field effect transistors, where the isolation structures between standard cells affect the performance of PMOS and NMOS transistors, leading to suboptimal speed and area efficiency.

Innovation Solution

The semiconductor device incorporates a combination of shallow and deep isolation patterns, with the shallow isolation patterns aligned with the deep isolation patterns, and gate electrodes intersecting these patterns, to create a diffusion barrier that isolates standard cells and optimizes the electrical characteristics of PMOS and NMOS transistors by varying the width and depth of these patterns based on the transistor type.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If shallow isolation patterns and deep isolation patterns are used to isolate standard cells, then electrical characteristics are improved, but device complexity increases

Engineering Contradiction:
Improveelectrical characteristicsVSAvoidisolation structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The isolation structure is divided into two distinct segments: shallow isolation patterns and deep isolation patterns. The shallow isolation patterns are formed at a first depth level while deep isolation patterns extend to a greater second depth level. This segmentation allows each isolation pattern type to serve specific electrical isolation functions, improving overall electrical characteristics without requiring a completely redesign of the isolation system.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different isolation patterns are applied to different regions based on specific electrical requirements. First shallow isolation patterns are disposed over first active regions while second shallow isolation patterns are disposed over second active regions, with each region receiving isolation treatment tailored to its specific electrical characteristics and performance needs.

Inventive Principle:
Principle #3Local quality

2Manufacturing precision

If isolation patterns are aligned between first and second active regions, then manufacturing precision is improved, but device complexity increases

Engineering Contradiction:
Improvealignment precisionVSAvoidpattern configuration complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The first shallow isolation patterns and second shallow isolation patterns are aligned with each other in the first direction, creating a merged isolation structure that spans across both first and second active regions. This alignment merges the isolation function across region boundaries, ensuring consistent electrical isolation characteristics while simplifying the manufacturing process through unified pattern registration.

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If deep isolation patterns divide the second active region, then electrical isolation is improved, but area efficiency deteriorates

Engineering Contradiction:
Improveisolation effectivenessVSAvoidstandard cell area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The deep isolation patterns extend vertically to a second depth level greater than the shallow isolation patterns, utilizing the depth dimension to achieve enhanced electrical isolation. By solving the isolation problem in the vertical dimension rather than requiring larger horizontal separation, the design maintains compact standard cell area while achieving effective electrical isolation between divided regions of the second active region.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS11404443B2Semiconductor device
Publication Date: 2022.08.02 SAMSUNG ELECTRONICS CO LTD
  • US11404443B2 patent drawing
  • US11404443B2 patent drawing
  • US11404443B2 patent drawing

AI summary

A semiconductor device includes a substrate including a first active region and a second active region, the first active region having a conductivity type that is different than a conductivity type of the second active region, and the first active region being spaced apart from the second active region in a first direction, gate electrodes extending in the first direction, the gate electrodes intersecting the first active region and the second active region, a first shallow isolation pattern disposed in an upper portion of the first active region, the first shallow isolation pattern extending in the first direction, and a deep isolation pattern disposed in an upper portion of the second active region, the deep isolation pattern extending in the first direction, and the deep isolation pattern dividing the second active region into a first region and a second region.