Semiconductor Apparatus Shared Pin Path Switching
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Solution Overview
Problem
In semiconductor packaging, it is challenging to accurately diagnose defects in system-in-package (SIP) configurations, where both the controller and stacked memory chips are sealed, as direct access to memory chips is necessary for troubleshooting, which complicates identifying whether defects are in the controller or the memory chips, and this requires additional pins that increase package size, hindering miniaturization.
Innovation Solution
A semiconductor apparatus that includes a path setting unit to selectively connect either the normal communication line or the test line to the memory based on the access mode, allowing for direct access during testing without the need for separate pins, thereby enabling shared signal transmission paths for both normal and direct access modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If direct access pins are added to enable direct access to memory chips for troubleshooting, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent combines direct access pins and normal access pins into a single shared pin structure. The same pin can function as either a direct access pin for test operations or a normal access pin for controller communication, depending on the access mode. This merging eliminates the need for separate pins, reducing package complexity while maintaining the ability to perform both direct memory access for troubleshooting and normal controller-mediated operations.
Solution Approach 2:
The patent implements multi-functionality by enabling pins to serve dual purposes: they can operate as direct access pins when test mode is activated, or as normal access pins when controller mode is active. This universal pin design allows the same physical infrastructure to support both troubleshooting operations and normal system operation, resolving the contradiction between measurement precision and device complexity.
2Measurement precision
If separate direct access pins are provided for memory access, then measurement precision is improved, but area of stationary object increases
Solution Approach 1:
The patent merges direct access pins and normal access pins into a single shared pin structure. This consolidation reduces the total number of pins required in the package, thereby reducing the package area occupied by pin connections while maintaining the capability for direct memory access during testing.
Solution Approach 2:
By designing pins with universal functionality that allows them to serve as either direct access pins or normal access pins depending on operational mode, the patent eliminates the need for additional dedicated pins. This multi-functionality directly reduces the package area required for pin infrastructure while preserving defect diagnosis capabilities.
3Measurement precision
If direct reception bumps are added to memories for direct signal reception, then measurement precision is improved, but volume of moving object increases
Solution Approach 1:
The patent extracts the direct signal reception capability from the memory chip itself and relocates it to the controller. The controller is equipped with direct transmission bumps that can directly transmit test signals to the memory chips without requiring the memory chips to have their own reception bumps. This extraction reduces memory chip volume while maintaining test operation capability.
Solution Approach 2:
The controller acts as an intermediary that provides direct access capability to the memory chips during testing. Instead of modifying the memory chips with reception bumps, the controller serves as the intermediary component that generates and transmits test signals directly to the memories through shared pins, eliminating the need for additional memory chip volume.
Data Source
AI summary
A semiconductor apparatus includes a controller, a memory, a normal line, a test line, and a path setting unit. The normal line is provided for communication between the controller and the memory. The test line is provided for a test operation of the memory. The path setting unit connects either the normal line or the test line to the memory according to a type of access mode.