3D Semiconductor Device Shared Global Word Line
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Solution Overview
Problem
The increasing number of stacked memory cells in 3D semiconductor devices leads to a complex layout of word lines, global lines, and transistors, resulting in excessive chip space consumption due to the need for separate local and global word lines for each transistor.
Innovation Solution
The arrangement of two transistors sharing a global word line, with a specific metal line structure that includes a first and second memory block, each with a word line multilayered structure, and local and global contact plugs to connect the transistors efficiently, reducing the number of global word lines and chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of stacked memory cells increases, then the storage capacity is improved, but the layout complexity and chip area consumption increase
Solution Approach 1:
The patent merges the functions of local word lines and global word lines by having transistors in different memory blocks share common global word lines. Specifically, transistors T1 and T2 share global word line GWL1, and transistors T3 and T4 share global word line GWL2, eliminating the need for separate local word lines in each memory block and reducing overall layout complexity
Solution Approach 2:
The global word lines serve multiple functions across different memory blocks. Each global word line is shared by transistors from multiple memory blocks (e.g., GWL1 serves both memory block MB1 and MB2), making the word line structure universal rather than dedicated to single blocks, thereby reducing the total number of word lines needed
2Reliability
If separate local and global word lines are provided for each transistor, then the transistor control functionality is improved, but the chip area consumption increases
Solution Approach 1:
The patent combines the word line functions by allowing transistors from different memory blocks to share the same global word line. This merging approach maintains full transistor control functionality while eliminating redundant local word lines, directly reducing chip area consumption
Solution Approach 2:
The patent transitions from a planar 2D layout with separate local and global word lines to a 3D stacked architecture where memory blocks are vertically arranged. This dimensional change allows transistors in different vertical layers to share horizontal word lines, reducing the footprint area while maintaining control functionality
Data Source
AI summary
A semiconductor device includes a first memory block and a second memory block in a cell region and a first transistor and a second transistor, respectively corresponding to the first and second memory blocks, in a pass transistor region located below the cell region, wherein each of the first and second transistors includes: a first gate electrode coupled to the first memory block and a second gate electrode coupled to the second memory block.