Semiconductor Sidewall Etching for Material Accumulation Removal

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Solution Overview

Problem

During semiconductor fabrication, the accumulation of material on sidewalls due to etching processes can lead to electrical leakage and manufacturing defects, as existing etching techniques do not effectively remove these accumulations without damaging underlying layers.

Innovation Solution

A subsequent etching process using a gas with fluorine as an etchant is employed to specifically target and remove the accumulated material on sidewalls, ensuring precise removal without compromising the integrity of the semiconductor device layers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional etching techniques are used to remove layers, then the etching process can effectively remove the targeted layer, but material accumulates on sidewalls causing electrical leakage and manufacturing defects

Engineering Contradiction:
Improveetching precisionVSAvoidsidewall material accumulation
Core Design Contradiction:
Manufacturing precisionVSObject-generated harmful factors

Solution Approach 1:

The etching process is divided into multiple sequential steps with different selectivities. The first etching step removes the primary layer while the second etching step specifically targets and removes the accumulated material on sidewalls. This segmentation allows each step to optimize for its specific function without interfering with the other.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent changes etching parameters between steps, including etchant composition, temperature, and pressure conditions. The first etching uses parameters optimized for removing the main layer, while the second etching uses different parameters specifically tuned to remove sidewall accumulations without affecting underlying layers.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If etching is performed to remove layers, then the desired layer removal is achieved, but underlying layers may be damaged or compromised

Engineering Contradiction:
Improvelayer removal efficiencyVSAvoidunderlying layer integrity
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The etching process is designed with spatial selectivity where the first etching step targets the upper layer while protecting underlying layers through controlled etch depth and selectivity ratios. The second etching step locally targets only the sidewall regions with minimal impact on horizontal areas, preserving underlying layer integrity while removing harmful accumulations.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The first etching step is performed as a preliminary action to remove the main layer before the second etching step addresses sidewall accumulations. This preliminary removal reduces the overall material load and allows the second step to focus specifically on sidewall cleanup without compromising underlying layers.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively mitigates electrical leakage by removing conductive accumulations, thereby enhancing the reliability and performance of semiconductor devices by maintaining the structural integrity of the layers.

Implementation Method 1

A subsequent etching process using a gas with fluorine as an etchant is employed to specifically target and remove the accumulated material on sidewalls

Methodology Applied
Scientific EffectEtching:

Data Source

PatentUS12014933B2Semiconductor device fabrication with removal of accumulation of material from sidewall
Publication Date: 2024.06.18 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12014933B2 patent drawing
  • US12014933B2 patent drawing
  • US12014933B2 patent drawing

AI summary

A method of fabricating a semiconductor device is provided. The method includes forming a first metal layer over a semiconductor substrate, and forming a first layer over the first metal layer. The first layer and first metal layer are etched to expose a sidewall of the first layer and a sidewall of the first metal layer, wherein the etching disburses a portion of the first metal layer to create an accumulation of material on at least one of the sidewall of the first layer or the sidewall of the first metal layer. At least some of the accumulation is etched away using an etchant comprising fluorine.