Semiconductor Device Slit Design for 3D Stack Alignment
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor devices with 3D cell strings, misalignment between contact plugs and channel structures occurs due to thermal stress causing bending of conductive patterns, which worsens as integration increases.
Innovation Solution
A semiconductor device design where a slit is formed through interlayer insulating and conductive patterns to divide them into stack structures, with the slit passing through a second interlayer insulating layer that protrudes higher than the stack structures, ensuring alignment between contact plugs and channel structures before forming the slit, thus preventing misalignment even when the layers bend under stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of interlayer insulating layers and conductive patterns is increased to enhance integration degree, then the degree of integration is improved, but the bending of conductive patterns becomes more severe due to thermal stress
Solution Approach 1:
The patent divides the continuous conductive patterns and interlayer insulating layers into separate stack structures by forming slits. This segmentation prevents the cumulative bending effect that would occur in continuous long-range conductive patterns under thermal stress, while still maintaining high integration through the stacked configuration.
Solution Approach 2:
The patent introduces slit insulating layers at specific locations (between stack structures) to provide localized stress relief and prevent bending. This allows the majority of the conductive patterns to maintain their stacked configuration for high integration, while only specific regions are modified to address the bending issue.
2Ease of manufacture
If the contact area between contact plug and channel structure is small, then the manufacturing process is simpler, but misalignment between contact plug and channel structure easily occurs during fabrication
Solution Approach 1:
The patent performs alignment of contact plugs with channel structures before the thermal stress that causes bending occurs. By establishing the correct positional relationship early in the fabrication process, the system compensates for subsequent dimensional changes without requiring larger contact areas or more complex alignment procedures.
Solution Approach 2:
By dividing the structure into discrete stack units separated by slits, the patent creates well-defined, localized regions where contact plugs can be precisely positioned. This segmentation provides clear reference points for alignment while maintaining simple contact plug formation processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces misalignment between contact plugs and channel structures, maintaining integration density without compromising the structural integrity of the 3D cell string under thermal stress.
Implementation Method 1
After forming the slit, thermal stress may be applied to the substrate. Due to the thermal stress, the conductive patterns may be bent.
Data Source
AI summary
The semiconductor device includes first interlayer insulating layers and first conductive patterns which are alternately stacked; a second interlayer insulating layer formed on the first interlayer insulating layers and the first conductive patterns; and a slit passing through the second interlayer insulating layer, the first interlayer insulating layers and the first conductive patterns to divide the first interlayer insulating layers and the first conductive patterns into stack structures.