Semiconductor Spacer Gap Filling via Vaporized Chemical Etching
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Solution Overview
Problem
Current semiconductor manufacturing processes face challenges in maintaining the height and width of spacers during subsequent deposition processes, often resulting in voids within gap filling materials due to the high aspect ratio gaps between protruding structures, which narrows the process window and leads to suboptimal device performance.
Innovation Solution
A semiconductor structure is developed with an interlayer dielectric layer having a specific gap profile, achieved through conformal deposition and vaporized chemical etching, which adjusts the top and bottom portions of the interlayer dielectric layer to maintain the desired aspect ratio and prevent voids during gap filling, thereby protecting spacer heights and widths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conformal deposition is used to fill high aspect ratio gaps between protruding structures, then the gap filling process becomes more challenging, but voids form within the gap filling material
Solution Approach 1:
The patent applies preliminary action by performing vaporized chemical etching on the interlayer dielectric layer before gap filling deposition. This pre-treatment modifies the gap profile by reducing the top portion and enlarging the opening, creating a more favorable geometry for subsequent material deposition that prevents void formation while maintaining the high aspect ratio structure.
Solution Approach 2:
The patent changes physical parameters of the gap profile through controlled vaporized chemical etching, specifically adjusting the aspect ratio, opening size, and top portion dimensions. These parameter modifications transform the gap geometry from a configuration prone to void formation to one that enables complete, void-free material deposition.
2Reliability
If the aspect ratio of gaps between protruding structures is increased to improve device performance, then device performance improves, but the process window for deposition narrows
Solution Approach 1:
The vaporized chemical etching step is performed in advance to optimize the gap profile before deposition. This preliminary modification of the gap geometry (reducing top portion, enlarging opening) creates a process window that accommodates high aspect ratio requirements while ensuring successful void-free deposition.
Solution Approach 2:
The patent modifies key geometric parameters of the gap (aspect ratio, opening dimension, top portion size) through controlled etching. These parameter changes enable the structure to maintain high aspect ratio for device performance while simultaneously creating favorable deposition conditions that widen the manufacturing process window.
3Manufacturing precision
If vaporized chemical etching is used to modify the interlayer dielectric layer, then the gap profile is optimized, but additional process steps are required
Solution Approach 1:
The patent replaces conventional wet chemical etching or mechanical polishing methods with vaporized chemical etching. This substitution provides superior profile control and precision through vapor-phase reaction mechanisms, enabling exact modification of the gap geometry (top portion reduction, opening enlargement) with better uniformity and less mechanical stress.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enlarges the deposition process window, ensuring void-free gap filling and maintaining spacer integrity, thus enhancing the performance and reliability of semiconductor devices.
Implementation Method 1
an interlayer dielectric layer is formed conformally over the gate structures and a surface of the silicon substrate
Implementation Method 2
a vaporized chemical etching operation is performed to etch the top portion of the interlayer dielectric layer
Data Source
AI summary
A method of manufacturing a semiconductor structure is provided. An interlayer dielectric layer is formed conformally over protruding structures formed over a silicon substrate and a surface of the silicon substrate. Next, a vaporized chemical etching operation is performed to the interlayer dielectric layer, so as to form a gap between two adjacent protruding structures. The gap has a target aspect ratio of at least 4, a top portion of the interlayer dielectric layer above an upper portion of each of the at least two protruding structures is trimmed at a first etching rate, and a bottom portion of the interlayer dielectric layer above a base portion of each of the at least two protruding structures is etched at a second etching rate smaller than the first etching rate, for enlarging the deposition process window and preventing voids from remaining inside a gap filling material in the gap.