Semiconductor Spacer Line Pattern Fabrication for Sub-50nm Holes
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Solution Overview
Problem
Current methods face challenges in forming small-sized patterns, such as holes of 50nm or less in diameter, due to limitations in exposing apparatus resolution, leading to complex fabrication processes, high production costs, and low yield in semiconductor device manufacturing.
Innovation Solution
A method involving sequential formation of mask layers and planarization layers, with specific materials like amorphous carbon and silicon oxynitride, and using photoresist patterns to create spacer line patterns for etching, allowing for the formation of high-density semiconductor devices with improved yield and reduced production costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional photolithographic exposing apparatus is used to form small holes, then the existing fabrication process can be maintained, but the resolution limitation prevents forming holes of 50nm or less in diameter
Solution Approach 1:
The patent divides the pattern formation process into multiple stages: first forming large photoresist patterns, then using spacer layers to create finer line patterns, and finally using etch masks to transfer the pattern. This multi-stage segmentation allows achieving sub-50nm precision that cannot be obtained through single-step photolithography.
Solution Approach 2:
The patent introduces vertical dimension by forming spacer layers on sidewalls of photoresist patterns. The spacer thickness, controlled by atomic layer deposition (ALD), determines the final pattern dimension. This moves the critical dimension control from lateral photolithography resolution to vertical thin film thickness control, enabling sub-50nm features.
2Manufacturing precision
If complex fabrication processes are adopted to overcome resolution limitations, then small-sized patterns can be formed, but production costs increase and production yield decreases
Solution Approach 1:
The spacer layers form self-aligned patterns on the sidewalls of photoresist structures. The spacer width is automatically determined by the spacer layer thickness and conformal deposition geometry, eliminating the need for additional alignment steps and reducing alignment errors that would降低 yield.
Solution Approach 2:
The patent changes the critical process parameter from photolithographic exposure resolution to atomic layer deposition thickness control. ALD provides atomic-level thickness control with low variability, enabling precise pattern dimensions and high production yield simultaneously.
3Manufacturing precision
If multiple mask layers and planarization layers are formed sequentially, then high-density patterns can be achieved, but the fabrication process complexity increases
Solution Approach 1:
The spacer layers serve multiple functions: they define the final pattern dimension through their thickness, provide self-alignment for subsequent etching, and act as etch masks during pattern transfer. This multi-functionality reduces the need for separate dedicated structures, simplifying the overall process despite multiple steps.
Solution Approach 2:
The planarization layers are formed in advance to create flat surfaces before subsequent patterning steps. This preliminary planarization ensures uniform thickness of deposited layers and consistent etching conditions, enabling high-density patterns without requiring complex in-situ adjustments during later processing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method simplifies the fabrication process, enhances production yield, and enables the creation of high-density semiconductor devices with smaller feature sizes, overcoming the limitations of existing technologies.
Implementation Method 1
forming first photoresist patterns on the second mask layer, forming the first lines on sidewalls of the first photoresist patterns
Implementation Method 2
etching the third mask layer and the first planarization layer, using the second lines as an etch mask, to form third mask line patterns and first planarization lines
Implementation Method 3
the first and second planarization layers may be formed of a spin-on-carbon (SOC) layer
Data Source
AI summary
A method of fabricating a semiconductor device may include forming spacer line patterns on sidewalls of photoresist. A planarization etching process may be performed on a subsequently added planarization layer, after forming a mesh-shaped mask pattern from the spacer line patterns.