3D Semiconductor Device Insulating Spacer Positioning
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Solution Overview
Problem
Current three-dimensional semiconductor memory devices face challenges in reducing electric resistance in current pathways, which affects memory capacity and efficiency, particularly due to limitations in pattern miniaturization and multi-level cell techniques.
Innovation Solution
The design incorporates a three-dimensional semiconductor device structure with conductive patterns, semiconductor patterns, and insulating spacers, where the insulating spacer's bottom surface is positioned at a vertical level equivalent to or higher than the uppermost surface of the lower structure, and includes a semiconductor core with an extended portion covering the sidewall of the spacer, reducing the distance and resistance in the current path.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If pattern miniaturization technique is used to increase memory capacity, then memory capacity increases, but manufacturing cost increases significantly
Solution Approach 1:
The patent transitions from two-dimensional planar memory structures to three-dimensional vertical structures by stacking multiple memory cell layers. Memory cells are arranged vertically with word lines extending in the vertical direction, enabling increased storage capacity without requiring further miniaturization of individual cell dimensions, thus avoiding the associated manufacturing cost increases
2Quantity of substance
If multi-level cell technique is used to increase memory capacity, then memory capacity increases per cell, but the number of bits per cell is limited
Solution Approach 1:
The patent divides the memory structure into multiple independent memory cell layers stacked vertically, with each layer containing complete memory cells. This segmentation allows the memory system to achieve increased capacity through vertical stacking rather than increasing bits per cell, maintaining simpler cell structures while achieving higher overall capacity
3Quantity of substance
If three-dimensional memory structure is implemented, then memory capacity increases, but electric resistance in current pathways increases
Solution Approach 1:
The patent implements a three-dimensional structure where bit lines and word lines are positioned to create direct vertical current pathways through the memory cell layer. The bit line is disposed at a first vertical position and the word line at a second vertical position, with the vertical channel extending between them, enabling short and direct current paths that minimize resistance despite the three-dimensional arrangement
Data Source
AI summary
A three-dimensional semiconductor device includes an upper structure on a lower structure, the upper structure including conductive patterns, a semiconductor pattern connected to the lower structure through the upper structure, and an insulating spacer between the semiconductor pattern and the upper structure, a bottom surface of the insulating spacer being positioned at a vertical level equivalent to or higher than an uppermost surface of the lower structure.