Semiconductor Stack Test Diode Circuits for Bonding Defect Detection

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Solution Overview

Problem

Current semiconductor device manufacturing methods face challenges in rapidly detecting shorts and opens during the bonding process, leading to delayed feedback and prolonged production timelines due to the inefficiency of existing verification methods, which are not real-time and require significant time for manual X-Ray analysis or build-in self-test procedures.

Innovation Solution

A connection structure with test diode circuits and non-releasable interconnections is integrated into the semiconductor device to enable real-time detection of defects by characterizing current paths and adjusting manufacturing parameters, allowing for immediate feedback and process adjustments during the Thermo Compression bonding process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If manual X-Ray analysis is used to verify inter-die connections, then measurement precision is improved, but loss of time increases significantly

Engineering Contradiction:
Improveinterconnect defect detection accuracyVSAvoidtime per unit for verification
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent replaces manual mechanical X-Ray analysis with an automated electrical test system that uses current paths and diode circuits to detect interconnect defects. This substitution of measurement methodology eliminates the time-consuming manual inspection process while maintaining defect detection capability through electrical characterization of the inter-die connections.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent implements a self-test capability where the semiconductor device uses its own integrated diode circuits and current paths to automatically verify interconnect health. This self-service approach eliminates the need for external manual X-Ray analysis, providing immediate feedback on inter-die connection quality without requiring separate verification equipment or personnel.

Inventive Principle:
Principle #25Self-service

2Productivity

If build in self-test (BIST) is used, then productivity is improved, but loss of time increases due to delayed data availability

Engineering Contradiction:
Improvethroughput of bonding processVSAvoiddelay in feedback data availability
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent performs the interconnect verification action during the bonding process itself rather than after completion. By integrating the electrical test into the manufacturing flow and using the bonding equipment to characterize current paths, the verification happens preliminarily before the device leaves the production line, eliminating the week-long delay associated with post-packaging BIST data analysis.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent establishes real-time feedback loops where test results from diode circuit characterization are immediately available to operators during the bonding process. This feedback mechanism allows for immediate process adjustments and eliminates the delayed feedback inherent in traditional BIST approaches, enabling same-day or same-shift verification and correction.

Inventive Principle:
Principle #23Feedback

3Loss of time

If integrated electrical connection structure with diode circuits is used, then loss of time is reduced, but device complexity increases

Engineering Contradiction:
Improvetime for defect detectionVSAvoidstructure of semiconductor device
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent designs the diode circuits and current paths to serve multiple functions: they are part of the normal device operation and simultaneously serve as test structures for interconnect verification. This multi-functionality approach allows the same electrical structures to be used for both device functionality and defect detection, minimizing additional complexity while enabling rapid electrical testing during manufacturing.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution enables real-time monitoring and adjustment of the bonding process, reducing the occurrence of defects and minimizing delays in product release by providing immediate feedback on interconnect health, thus enhancing the efficiency and speed of semiconductor device production.

Implementation Method 1

an electrical connection structure electrically conductively coupling the first contact and the second contact with each other via at least one non-releasable interconnection of the non-releasable interconnections; wherein the electrical connection structure includes a plurality of test diode circuits integrated in at least one of the carrier and the semiconductor device

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Data Source

PatentEP4336195A1Product design for test to enable electrical non-destructive test for measuring multi-chip interconnect defects
Publication Date: 2024.03.13 INTEL CORP
  • EP4336195A1 patent drawingFigure 1
  • EP4336195A1 patent drawingFigure 2A~2B
  • EP4336195A1 patent drawingFigure 2C

AI summary

A semiconductor stack (100), including a carrier (101) and a semiconductor device (102) arranged above the carrier (191; non-releasable interconnections (103) electrically and mechanically connecting the semiconductor device (102) and the carrier (101); a first contact (230) on at least one of the carrier (101) or the semiconductor device (102); a second contact (232) on at least one of the carrier (191) or the semiconductor device (102); an electrical connection structure electrically conductively coupling the first contact (230) and the second contact (232) with each other via at least one non-releasable interconnection of the non-releasable interconnections (103); and wherein the electrical connection structure comprises a plurality of test diode circuits (402) integrated in at least one of the carrier (101) and the semiconductor device (102), wherein each of the test diode circuits (402) comprises one or more diodes.