Semiconductor Stack Gate Overlap for Reliability
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Solution Overview
Problem
Current three-dimensional semiconductor devices face challenges in enhancing operational reliability due to limitations in the design and manufacturing methods, particularly in the integration of stack structures and contact lines, which affect the performance of memory cell transistors and select transistors.
Innovation Solution
The semiconductor device incorporates a stack structure with horizontal conductive patterns and interlayer insulating layers alternately stacked, featuring gate patterns that overlap with the end regions of the stack structures, source and well contact lines, and a channel pattern with vertical parts penetrating the stack structure, along with a connection part connecting the vertical parts, to improve reliability and integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate patterns overlap with the entire stack structure, then good contact is achieved, but resistance increases and turn-on current decreases
Solution Approach 1:
The gate pattern is designed to overlap only with the end region of the stack structure rather than the entire stack, creating local differentiation in the electrical characteristics. This localized overlap reduces resistance in the source select line while maintaining adequate contact for reliable operation.
Solution Approach 2:
The stack structure is functionally segmented into an end region (where gate overlap occurs) and a non-end region (where gate does not overlap). This segmentation allows different portions of the stack to serve different functions: the end region provides good electrical contact while the non-end region maintains low resistance.
2Reliability
If source contact line is positioned to improve contact, then reliability improves, but resistance control becomes difficult
Solution Approach 1:
The source contact line is positioned to protrude toward the well structure before final device operation, establishing optimal electrical contact in advance. This preliminary positioning ensures reliable contact while the specific geometric configuration pre-determines the resistance characteristics.
Solution Approach 2:
The source contact line extends in multiple dimensions: it protrudes toward the well structure in the vertical dimension while also having lateral extension. This multi-dimensional configuration allows simultaneous optimization of contact reliability and resistance control.
3Adaptability or versatility
If channel layer extends to space between well structure and stack structures, then device integration improves, but manufacturing complexity increases
Solution Approach 1:
The channel layer extends into the third dimension by reaching into the space between the well structure and stack structures. This vertical extension into previously unused space enables better device integration without requiring additional lateral manufacturing steps.
Solution Approach 2:
The channel layer serves multiple functions: it provides the conductive path for current flow, extends into the interstitial space for better integration, and connects the vertical parts of the stack structure. This multi-functionality reduces the need for separate components.
Data Source
AI summary
A semiconductor device includes: a stack structure including horizontal conductive patterns and interlayer insulating layers, which are alternately stacked; gate patterns overlapping with both ends of the stack structure under the stack structure, the gate patterns being spaced apart from each other; and a channel pattern including vertical parts penetrating the stack structure, and a connection part disposed under the stack structure, the connection part connecting the vertical parts.