Semiconductor Stack Structure Fabrication Using Wafer Rearrangement
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Solution Overview
Problem
The rapid miniaturization of electronic products necessitates the integration of wafers of different specifications, which requires new equipment and factory setups, hindering the timely supply of chip packages due to the need for specialized process equipment for each wafer size.
Innovation Solution
A semiconductor stack structure fabrication method involving wafer singulation, rearrangement, and bonding to a substrate, using carriers and positioning elements to expose conductive pads, form vias, and create redistribution layers, allowing wafers of one specification to be processed using conventional equipment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If wafers of different specifications are integrated to meet miniaturization requirements, then multi-function and miniaturization are achieved, but new equipment and factory setups are required, increasing device complexity and fabrication costs
Solution Approach 1:
The patent segments the wafer processing into two independent stages: first, singulating chips from wafers of any specification using existing equipment; second, rearranging and bonding these singulated chips into stack structures. This segmentation allows each stage to use conventional equipment independently, eliminating the need for specialized processing equipment for each wafer size while achieving miniaturization through vertical stacking.
Solution Approach 2:
The patent transitions from planar wafer processing to three-dimensional stack structure assembly. By singulating chips and then bonding them vertically into stacks, the invention achieves miniaturization in the vertical dimension while using conventional two-dimensional processing equipment, thus resolving the contradiction between miniaturization and equipment complexity.
2Manufacturing precision
If specialized process equipment is used for each wafer specification, then processing precision is maintained, but productivity decreases due to inability to meet replacement speed of electronic products
Solution Approach 1:
The patent separates the processing into singulation and assembly stages, allowing conventional equipment to maintain precision during chip fabrication while enabling rapid reconfiguration during the assembly stage to meet changing product requirements, thus maintaining both precision and productivity.
Solution Approach 2:
The invention introduces dynamic flexibility at the assembly stage where chips can be rearranged and stacked in different configurations based on product requirements. This dynamic approach allows rapid adaptation to new electronic products without requiring new specialized equipment, maintaining productivity while meeting diverse precision requirements through proven conventional processes.
3Adaptability or versatility
If new equipment and factory buildings are developed for new electronic products, then processing capability is improved, but time for timely supply increases, affecting product replacement speed
Solution Approach 1:
The patent performs preliminary singulation of chips from wafers using existing equipment before the need for new products arises. These singulated chips can be stored and rapidly assembled into new stack structures when new electronic products are developed, eliminating the time required to develop new equipment and factories while maintaining adaptability to new product requirements.
Solution Approach 2:
By moving to three-dimensional stack assembly using conventional two-dimensional equipment, the invention achieves rapid adaptability to new products without the time-consuming development of new specialized equipment, thus reducing supply time while maintaining processing capability.
4Ease of manufacture
If wafers are processed using existing equipment, then fabrication costs are reduced, but the ability to process different specifications is limited
Solution Approach 1:
The patent segments wafer processing into chip singulation and stack assembly stages. At the singulation stage, existing equipment processes wafers of any specification at conventional costs. At the assembly stage, chips are rearranged and bonded into stacks, providing specification flexibility without requiring expensive specialized equipment for each wafer size, thus maintaining low fabrication costs while achieving adaptability.
Data Source
AI summary
A fabrication method of a semiconductor stack structure mainly includes: singulating a wafer of a first specification into a plurality of chips; rearranging the chips into a second specification of a wafer so as to stack the chips on a substrate of the second specification through a plurality of blocks; forming a redistribution layer on the chips; and performing a cutting process to obtain a plurality of semiconductor stack structures. Therefore, the present invention allows a wafer of a new specification to be processed by using conventional equipment without the need of new factory buildings or equipment. As such, chip packages can be timely supplied to meet the replacement speed of electronic products.