Semiconductor Device Inductance Reduction via Stacked Circuit Units
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Solution Overview
Problem
In power semiconductor modules, fast switching operations lead to overvoltage breakdown and noise due to high inductance, and while reducing inductance can slow switching, it increases switching loss; existing methods fail to effectively suppress overvoltage and loss simultaneously.
Innovation Solution
A semiconductor device comprising multiple circuit units with switching elements and capacitors arranged in a specific configuration to reduce inductance by adjacent placement of switching and capacitor elements, thereby minimizing mutual inductance and enhancing current distribution uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If switching time is extended to suppress overvoltage, then overvoltage is reduced, but switching operation becomes slow and switching loss increases
Solution Approach 1:
The power semiconductor module is divided into multiple circuit units (first circuit unit, second circuit unit, etc.) with separate switching elements and capacitors. This segmentation reduces the overall inductance of the module by distributing the current paths, allowing fast switching operation while suppressing overvoltage. Each circuit unit operates semi-independently, reducing the di/dt-induced overvoltage without sacrificing switching speed.
2Loss of energy
If inductance is reduced to suppress overvoltage and reduce switching loss, then overvoltage and loss are suppressed, but device complexity increases
Solution Approach 1:
Capacitor portions are stacked adjacent to switching element portions within the same circuit unit, and circuit units are arranged with alternating patterns (switching element portion of one unit adjacent to capacitor portion of another unit). This merging of functional elements in three-dimensional space reduces the overall module inductance and complexity compared to traditional separate layouts, while maintaining low switching loss through reduced di/dt.
3Reliability
If switching elements and capacitors are arranged adjacently to reduce inductance, then inductance is reduced and overvoltage is suppressed, but manufacturing precision requirements increase
Solution Approach 1:
The module transitions from a two-dimensional planar layout to a three-dimensional stacked configuration. Capacitor portions are positioned in the vertical dimension adjacent to switching element portions, and multiple circuit units are arranged in alternating patterns across different layers. This dimensional change reduces inductance while providing manufacturing tolerance through the additional spatial degree of freedom.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces inductance, suppresses overvoltage and noise generation, and improves current distribution uniformity, leading to reduced manufacturing costs and enhanced reliability in semiconductor modules.
Implementation Method 1
a capacitor portion including a capacitor electrically connected in parallel to the first switching element and the second switching element between the first electrode and the second electrode
Implementation Method 2
The overvoltage during the turn-off time is proportional to a time change rate between inductance inside circuit wiring and current flowing in the power semiconductor module (di/dt)
Data Source
AI summary
A semiconductor device according to an embodiment includes a plurality of circuit units each includes a first electrode, a second electrode, a switching element portion including first and second switching elements electrically connected between the first electrode and the second electrode, and a capacitor portion including a capacitor electrically connected between the first electrode and the second electrode and stacked with the switching element portion. In two of the adjacent circuit units, the switching element portion of one circuit unit and the capacitor portion of the other circuit unit are adjacent to each other, the capacitor portion of the one and the switching element portion of the other are adjacent to each other, the first electrode of the one and the first electrode of the other are adjacent to each other, and the second electrode of the one and the second electrode of the other are adjacent to each other.