Semiconductor Storage Device Air Gap Isolation
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Solution Overview
Problem
The increasing demand for microfabrication in semiconductor storage devices leads to higher parasitic capacitance due to narrower gate widths and lengths, causing degradation in data reliability, and existing methods for reducing capacitive coupling through air gaps are ineffective in maintaining structural strength.
Innovation Solution
A method of manufacturing semiconductor storage devices that involves forming air gaps in the element isolation region by using a sacrificial polysilazane film, which is then removed to create unfilled gaps between memory-cell gate electrodes, while using a TEOS film to enclose the trenches and prevent refilling, thereby reducing coupling capacitance and maintaining structural integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If air gaps are formed in the element isolation region by removing sacrificial film, then coupling capacitance between memory-cell gate electrodes is reduced, but the structural strength of the element isolation region deteriorates
Solution Approach 1:
The patent applies local quality by selectively filling only the element isolation trench at the semiconductor substrate level with insulating film, while leaving the trenches between memory-cell gate electrodes unfilled to maintain air gaps. This localized differentiation allows the substrate-level isolation to gain structural strength from the insulating film, while the gate-level air gaps continue to reduce coupling capacitance effectively.
Solution Approach 2:
The patent segments the isolation structure into two distinct levels: (1) element isolation trench at the semiconductor substrate level filled with insulating film for structural support, and (2) trenches between memory-cell gate electrodes left unfilled to maintain air gaps for capacitance reduction. This segmentation allows each level to perform its specific function optimally without interfering with the other.
2Strength
If insulating film is formed to enclose air gaps, then structural strength is improved, but air gaps are refilled by the insulating film causing capacitance to increase
Solution Approach 1:
The patent applies preliminary action by forming the insulating film selectively in the element isolation trench at the substrate level before forming the memory-cell gate electrodes. This preliminary isolation structure provides structural strength upfront, enabling subsequent processes to leave air gaps unfilled without compromising overall structural integrity. The pre-formed insulating film acts as a foundational support that prevents the need to enclose air gaps with additional film layers.
3Productivity
If gate width and gate length are narrowed for microfabrication, then device density is improved, but parasitic capacitance increases leading to data reliability degradation
Solution Approach 1:
The patent extracts the harmful dielectric material from the spaces between memory-cell gate electrodes by maintaining air gaps at the gate level. This removal of insulating film from critical areas eliminates the source of parasitic capacitance that would otherwise couple adjacent narrow gate electrodes. The extraction is achieved by selective filling only at the substrate level while leaving gate-level trenches unfilled, thereby reducing parasitic capacitance and improving data reliability despite narrower gate dimensions.
Data Source
AI summary
Method of manufacturing a semiconductor device includes forming, in a first region, a first trench through a second gate electrode film and an interelectrode insulating film, and a second trench partially extending into a sacrificial film in an isolation trench, filling the second trench with a first insulating film; forming a third gate electrode film above the second gate electrode film and into the first trench such that the third gate electrode film contacts the first gate electrode film; etching the third and the second gate electrode film, the interelectrode insulating film, and the first gate electrode film to form select gate electrodes in the first region and a group of memory-cell gate electrodes in the second region; removing the sacrificial film; and forming a second insulating film over the element regions and the isolation trench to define an unfilled gap in the isolation trench below the memory-cell gate electrodes.