Semiconductor Storage Device Current Alignment for Faster NAND Writing
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Solution Overview
Problem
The writing speed in NAND memory is slowed due to the need for verification reading processes.
Innovation Solution
The semiconductor storage device employs a sense amplifier module that controls the direction of current flow during writing and reading operations to align with the direction of data verification, using Normal Order Program (NOP) and Reverse Order Program (ROP) methods, and Sub-Block Mode (SBM) to optimize writing speed by reducing parasitic resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If verification reading is performed during data writing to memory cells, then data accuracy is ensured, but writing speed becomes slow
Solution Approach 1:
The patent dynamically changes the direction of current flow during writing operations to match the direction during reading operations. By making the writing current direction variable and adaptive (either from source line to bit line or vice versa), the system eliminates the need for verification reading, thus maintaining data accuracy while improving writing speed
Solution Approach 2:
The patent changes the parameter of current flow direction during writing operations. By controlling the writing current to flow in the same direction as the reading current (either source line to bit line or bit line to source line), the patent modifies the writing process parameter to eliminate verification requirements, thereby resolving the contradiction between reliability and productivity
Data Source
AI summary
In one embodiment, a semiconductor storage device includes a string that has one end electrically connected to a bit line, and another end electrically connected to a source line, and includes a plurality of memory cells. An operation of writing data to each of a plurality of adjacent first memory cells among the plurality of memory cells is sequentially performed in a direction from a first memory cell on a side of the source line to a first memory cell on a side of the bit line. An operation of reading data from each of the plurality of adjacent first memory cells is performed to allow a current to flow through the string in a first direction from the source line to the bit line.