Semiconductor Storage Device Defective Column Handling
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Solution Overview
Problem
Existing semiconductor storage devices face inefficiencies in data input/output due to defective columns, which reduce the interleave efficiency and hinder high-speed access when multiple defective columns are present, leading to a decrease in overall performance.
Innovation Solution
A semiconductor storage device with a redundant array that can replace defective columns, a cache memory for data storage, a defective column storage module, and a clock generator that dynamically switches access between the cell array and redundant array to maintain consistent interleave operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a defective column is detected in a divided page buffer area, then access is redirected to another divided page buffer area, but the number of interleaves decreases and interleave efficiency deteriorates
Solution Approach 1:
The patent introduces a clock generator as an intermediary component that mediates between the defective column detection and the page buffer access. When a defective column is detected, the clock generator dynamically adjusts clock signals to redirect access to a different divided page buffer area, thereby maintaining the interleave operation flow without interruption. This intermediary mechanism allows the system to handle defective columns while preserving interleave efficiency.
Solution Approach 2:
The patent implements dynamic adjustment of clock signals based on defective column detection. The clock generator dynamically changes the timing and routing of clock signals to different divided page buffer areas depending on which columns are defective. This dynamic behavior allows the system to adapt to different defect patterns while maintaining a consistent number of interleaves, thus resolving the contradiction between reliability and productivity.
2Reliability
If access is redirected away from divided page buffer areas containing defective columns, then data access continues, but the cycle time increases and high-speed data input/output cannot be achieved
Solution Approach 1:
The patent employs periodic clock signals to access divided page buffer areas in an interleaved manner. When a defective column is detected, the clock generator modifies the periodic clock signals to skip the affected area and access alternative areas, maintaining the periodic rhythm of access operations. This periodic action ensures continuous data access while minimizing time loss by keeping the overall access rhythm intact.
Solution Approach 2:
The patent ensures continuous data input/output operations by dynamically redirecting clock signals to alternative divided page buffer areas when defective columns are detected. The clock generator maintains the continuity of useful action by preventing interruptions in the data access sequence, thereby avoiding increases in cycle time while ensuring reliable data access despite column defects.
3Reliability
If the number of interleaves varies due to defective columns, then defective columns are handled, but interleave efficiency decreases and access speed reduces
Solution Approach 1:
The patent changes the parameters of clock signals dynamically based on defective column detection. The clock generator adjusts clock frequency, phase, and routing parameters to maintain a constant number of interleaves even when defective columns are present. By changing these parameters adaptively, the system preserves access speed while handling defective columns effectively.
Solution Approach 2:
The patent implements a feedback mechanism where the detection of defective columns feeds back to the clock generator, which then adjusts clock signal routing accordingly. This closed-loop feedback ensures that the number of interleaves remains constant by dynamically compensating for defective columns through real-time clock signal modification, thereby maintaining high access speed while ensuring reliable data access.
Data Source
AI summary
A semiconductor storage device has a cell array, a redundant array provided logically separated from the cell array, a cache memory having a storing area of data read from or written in the cell array by one access, defective column storage to store a column address of a defective column in the cell array, a defective column determination module to determine whether a column address to be accessed matches the column address stored in the defective column storage, and a clock generator to generate a clock for accessing each of the divided areas for each period of the interleave access and, when the defective column determination module determines that there is a match, instead of a clock accessing a divided page buffer area at the generation timing of the clock accessing the divided page buffer area.