Semiconductor Storage Device Two-Axis Read Error Reduction

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Solution Overview

Problem

Existing semiconductor storage devices face challenges in accurately reading data due to the likelihood of read errors when determining the states of variable resistance elements using a single axial direction, such as current or voltage, which can lead to incorrect determination of resistance states.

Innovation Solution

A semiconductor storage device with a memory cell configuration that includes two variable resistance elements connected in series, utilizing distinct threshold currents and voltages to determine their states through a two-stage read operation, focusing on the current-voltage characteristic to minimize read errors by comparing read currents with reference currents and voltages.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If a single axial direction (current or voltage) is used to determine the state of variable resistance elements, then the reading operation is simple, but read errors occur due to incorrect determination of resistance states

Engineering Contradiction:
Improvereading operation simplicityVSAvoiddata reading accuracy
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The patent transitions from single-axial (one-dimensional) reading to two-axial (two-dimensional) reading by simultaneously measuring both voltage and current characteristics. This dimensional expansion allows accurate determination of resistance states by comparing the product of voltage and current against reference values, eliminating read errors that occur with single-axial measurement.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Quantity of substance

If multiple variable resistance elements are used in one memory cell to increase storage capacity, then storage capacity is improved, but the complexity of determining the state of each element increases

Engineering Contradiction:
Improvestorage capacityVSAvoidstate determination complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent merges the measurement of multiple variable resistance elements into a single unified measurement process. By measuring the combined voltage and current characteristics of the memory cell and calculating the product, the system can determine the states of multiple elements simultaneously without requiring separate measurement circuits for each element, thus maintaining simplicity while supporting high storage capacity.

Inventive Principle:
Principle #5Merging (Combining)

3Measurement precision

If two-stage read operation with multiple reference values is used, then reading accuracy is improved, but the reading process becomes more complex

Engineering Contradiction:
Improveresistance state determination accuracyVSAvoidread operation complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent performs preliminary classification by comparing the product of voltage and current against a first reference value to determine if the memory cell is in a high-resistance or low-resistance state. Based on this preliminary result, the system selectively applies the appropriate second reference value for final state determination. This staged approach with preliminary action improves accuracy while managing complexity through conditional logic.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces the likelihood of read errors by determining data states in multiple stages across both voltage and current axes, enhancing the accuracy of data retrieval in semiconductor storage devices.

Implementation Method 1

a first variable resistance element changeable from a first state to a second state at which a resistance value of the first variable resistance element is higher than that of the first variable resistance element at the first state, and a second variable resistance element connected to the first resistance-variable element in series and changeable from a third state to a fourth state at which a resistance value of the second variable resistance element is higher than that of the second variable resistance element at the third state

Methodology Applied
Scientific EffectVariable resistance: Electrical Resistance

Implementation Method 2

in the memory cell, a first snapback occurs at a first threshold current and a first threshold voltage, and a second snapback occurs at a second threshold current that is greater than the first threshold current and a second threshold voltage that is greater than the first threshold voltage

Methodology Applied
Scientific EffectSnapback effect:

Data Source

PatentUS10734075B2Semiconductor storage device and method of reading data therefrom
Publication Date: 2020.08.04 KIOXIA CORP
  • US10734075B2 patent drawing
  • US10734075B2 patent drawing
  • US10734075B2 patent drawing

AI summary

A semiconductor storage device includes a memory cell having a first variable resistance element changeable from a first state to a second state at which a resistance value of the first variable resistance element is higher than that of the first variable resistance element at the first state, and a second variable resistance element connected to the first variable resistance element in series and changeable from a third state to a fourth state at which a resistance value of the second variable resistance element is higher than that of the second variable resistance element at the third state. In the memory cell, a first snapback occurs at a first threshold current and a first threshold voltage, and a second snapback occurs at a second threshold current that is greater than the first threshold current and a second threshold voltage that is greater than the first threshold voltage.