Semiconductor Storage Device Global Word Line Segmentation
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Solution Overview
Problem
The increasing number of bit lines and word lines in semiconductor storage devices leads to a larger arrangement area for decoders, making it difficult to control voltages on non-selected lines effectively, which can result in reduced controllability and flexibility, and potentially cause unintended voltage application to non-selected memory cells.
Innovation Solution
The semiconductor storage device employs a configuration with global signal lines, selection signal lines, and bypass transistors to manage voltage application, ensuring that non-selected word lines are kept at a non-selection voltage, reducing the influence of selection voltage on them and preventing unintended writing to memory cells, while minimizing the number of global word lines required.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of bit lines and word lines is increased to expand storage capacity, then the storage capacity is improved, but the arrangement area of the decoder increases
Solution Approach 1:
The patent divides the word lines into multiple groups, with each group controlled by a separate selection signal line. This segmentation allows the decoder to control multiple word lines using fewer transistors, reducing the decoder area while maintaining the ability to address individual word lines within each group.
Solution Approach 2:
The patent introduces a hierarchical control structure where selection signal lines control groups of word lines, and global word lines provide additional addressing capability. This multi-dimensional control approach enables expanded storage capacity without proportionally increasing decoder area.
2Area of stationary object
If transistors are simply omitted from the multiplexer to reduce arrangement area, then the decoder area is reduced, but the controllability and flexibility of voltage application to bit lines or word lines are reduced
Solution Approach 1:
The patent segments the control function into multiple components: selection signal lines for group-level control and global word lines for individual line control. This segmentation maintains voltage controllability and flexibility while using fewer transistors overall, as each control path is simplified but the hierarchical structure preserves functionality.
Solution Approach 2:
The patent introduces global word lines as intermediary elements that work in conjunction with selection signal lines. These global word lines act as mediators that enable fine-grained voltage control without requiring full transistor control for each individual word line, thus maintaining controllability while reducing area.
3Area of stationary object
If transistors are omitted from the multiplexer to reduce arrangement area, then the decoder area is reduced, but it becomes difficult to appropriately control the voltage of non-selected bit lines or word lines
Solution Approach 1:
The patent segments the voltage control function across multiple control paths: selection signal lines control groups of lines, while global word lines provide additional control for non-selected lines. This segmented approach ensures that even with fewer transistors per control path, the combined system maintains reliable voltage control for both selected and non-selected lines.
Solution Approach 2:
The global word lines serve as intermediary control elements that enable reliable voltage control of non-selected lines. By working in conjunction with the selection signal lines, these intermediaries ensure that non-selected lines receive appropriate voltage levels, maintaining control reliability while reducing the total transistor count.
Data Source
AI summary
A memory includes first signal-lines divided into groups. Global signal lines correspond to the first signal-lines. The global signal-lines include a selected global signal-line and a non-selected global signal-line. First transistors correspond to the first signal-lines. The first transistors are connected between a corresponding first signal-line and any of the global signal-lines. Selection signal-lines correspond to the groups. The selection signal-lines are connected to gate electrodes of the first transistors included in a corresponding group. Second transistors are connected between the first signal-lines that belong to adjacent two of the groups. When one of the first signal-lines which is electrically connected to the selected global signal-line is a selected first signal-line, the first transistors corresponding to one of the groups which includes the selected first signal-line is in a conducting state. One of the second transistors which is connected to the selected first signal-line is in a non-conducting state.