Semiconductor Storage Device Leakage Current Control
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Solution Overview
Problem
Memory blocks in semiconductor devices experience leakage current when local lines of unselected memory blocks are set to a floating state, leading to operational failures and reliability degradation during data input or output operations.
Innovation Solution
The semiconductor device incorporates a memory array with memory blocks featuring pipe transistors, drain select transistors, and source select transistors, along with a gate control circuit that manages the gates of unselected memory blocks to prevent leakage current by applying appropriate voltages and controlling the pipe transistor, drain select transistor, and source select transistor during program and read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If local lines of unselected memory blocks are set to a floating state during data input or output operations, then the operation circuit can focus on the selected memory block, but leakage current flows between bit line and common source line causing operational failures and reliability degradation
Solution Approach 1:
The gate control circuit applies a predetermined voltage (e.g., ground potential or negative voltage) to the gate of the pipe transistor in unselected memory blocks before data input or output operations begin. This preliminary action creates a reverse bias condition that prevents leakage current from flowing between the bit line and common source line, thereby eliminating the reliability issue while maintaining high operation speed for selected blocks
Solution Approach 2:
The invention changes the voltage parameter of the pipe transistor gate from a floating state (high impedance) to an actively controlled voltage state (ground or negative potential). This parameter change transforms the electrical characteristics of the unselected memory blocks, ensuring they remain electrically isolated and prevent leakage current paths while allowing the selected block to operate at full speed
2Reliability
If a gate control circuit is added to control the pipe transistor of unselected memory blocks, then leakage current is blocked and reliability is improved, but device complexity increases
Solution Approach 1:
The gate control circuit is designed to control multiple pipe transistors across numerous unselected memory blocks using a single control line or a small set of control signals. This multi-functional approach allows one control circuit to manage the leakage prevention for many memory blocks simultaneously, thereby improving reliability without proportionally increasing device complexity
Solution Approach 2:
The control of pipe transistors in unselected memory blocks is merged with the existing block selection logic. The same control signals used to select active memory blocks are also used to control the pipe transistors, combining two functions into a unified control scheme that reduces overall circuit complexity while maintaining reliability
Data Source
AI summary
A semiconductor device includes a memory array including a plurality of memory blocks. Each memory block includes a pipe transistor, a drain select transistor and a first memory cell connected between the pipe transistor and a bit line, and a source select transistor and a second memory cell connected between the pipe transistor and a common source line. The semiconductor device further includes an operation circuit configured to apply an operating voltage to a memory block selected to perform program and read operations, and a gate control circuit configured to control a gate of the pipe transistor included in an unselected memory block.