Semiconductor Storage Device Adaptive Program Voltage Control
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Solution Overview
Problem
Current semiconductor storage devices face challenges in achieving high-speed operation due to variations in memory cell transistor characteristics, which affect writing efficiency and reliability.
Innovation Solution
The semiconductor storage device employs a controller that determines program voltages for word lines based on the number of loops required during write operations on different memory cell transistors, optimizing the write process by storing count values in a writing information register to adjust program voltages accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a uniform program voltage is applied to all word lines, then the device structure and control logic are simple, but variations in memory cell transistor characteristics cause writing inefficiency and reliability issues
Solution Approach 1:
The patent applies local quality by assigning different program voltages to different word lines based on their specific memory cell characteristics. The controller identifies word lines with abnormal writing characteristics and applies adjusted program voltages specifically to those word lines, rather than using a uniform voltage for all word lines. This localized adjustment improves writing reliability for affected word lines while maintaining simplicity for the majority of normal word lines.
Solution Approach 2:
The patent changes the program voltage parameter dynamically based on the writing characteristics of each word line. The controller monitors writing results and adjusts the program voltage magnitude or pulse width for specific word lines that exhibit abnormal characteristics, such as requiring higher voltages due to threshold voltage shifts or lower voltages to avoid over-programming. This parameter adaptation resolves the contradiction by optimizing reliability where needed.
2Reliability
If multiple software program loops are executed to accommodate variations in memory cell characteristics, then writing reliability improves, but operation speed decreases
Solution Approach 1:
The patent implements preliminary action by performing a characterization phase before normal writing operations, where the controller determines the optimal program voltage for each word line in advance. This preliminary calibration stores the optimal voltage parameters that can be directly applied during subsequent writing operations, eliminating the need for multiple iterative loops during actual data writing. The one-time characterization improves operation speed while ensuring reliable writing through pre-optimized parameters.
Solution Approach 2:
The patent uses feedback mechanisms where the controller monitors writing results in real-time and adjusts program voltage parameters based on verify operations. When writing abnormalities are detected, the controller immediately adjusts the program voltage for affected word lines and re-attempts the write operation, rather than executing multiple fixed loops. This adaptive feedback approach reduces the average number of loops needed while maintaining high writing reliability.
3Reliability
If the program voltage is increased to ensure reliable writing across all memory cells, then writing reliability improves, but the risk of over-programming and cell degradation increases
Solution Approach 1:
The patent applies local quality by determining appropriate program voltages for each individual word line based on its specific characteristics rather than using a high uniform voltage for all word lines. Word lines with normal characteristics receive standard program voltages, while only word lines with confirmed writing difficulties receive elevated voltages. This localized approach ensures reliable writing for problematic cells without subjecting healthy cells to degrading high voltages.
Solution Approach 2:
The patent implements partial action by applying elevated program voltages only to the extent necessary for each specific word line. The controller performs verify operations after each write attempt and stops increasing voltage once successful writing is achieved, avoiding excessive voltage application. This partial adjustment approach maintains reliability for difficult-to-program cells while preventing over-programming and degradation of cells that require standard voltages.
Data Source
AI summary
A semiconductor storage device includes first and second memory cell transistors at opposite sides of a first semiconductor body, third and fourth memory cell transistors at opposite sides of a second semiconductor body, a first word line connected to gates of the first and third memory cell transistors, a second word line connected to gates of the second and fourth memory cell transistors, and a controller. During a program operation on the third memory cell transistor, the controller determines a program voltage on the basis of a first number of loops determined during the write operation performed on the first memory cell transistor, and during a program operation on the fourth memory cell transistor, the controller determines a program voltage on the basis of a second number of loops determined during the write operation performed on the second memory cell transistor.