Semiconductor Storage Device Vertical Stacking Layout
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor storage devices face challenges in reducing the area required for peripheral circuits, leading to increased device size and longer connection paths with higher connection resistance due to the placement of column selection circuits and word line driving circuits in the same stacked portion as sense amplifiers.
Innovation Solution
The semiconductor storage device design includes a stacked portion with peripheral circuits such as column selection circuits and segment word line driving circuits positioned above the sense amplifiers, allowing for reduced area usage and shorter connection paths by separating these components vertically, utilizing field effect transistors with oxide semiconductor channel layers for reduced leakage current and thermal stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If column selection circuits and word line driving circuits are placed in the same stacked portion as sense amplifiers, then device integration is achieved, but the area required for peripheral circuits increases and connection paths become longer with higher connection resistance
Solution Approach 1:
The patent applies vertical stacking to separate peripheral circuits into different stacked portions. Sense amplifiers are placed in a first stacked portion while column selection circuits and word line driving circuits are placed in a second stacked portion above the first. This three-dimensional arrangement reduces the planar area required for peripheral circuits while shortening connection paths and reducing connection resistance compared to conventional two-dimensional layouts.
2Length of stationary object
If peripheral circuits are concentrated in a single stacked portion, then device integration is simplified, but connection paths become longer resulting in higher connection resistance
Solution Approach 1:
By vertically stacking peripheral circuits in multiple stacked portions, the patent reduces the horizontal distance between connected components. The column selection circuits and word line driving circuits in the second stacked portion are positioned closer to the memory cell array, thereby shortening connection paths and reducing connection resistance, which improves data retention reliability.
3Ease of manufacture
If sense amplifiers and column selection circuits are placed in the same stacked portion, then manufacturing process is simplified, but the overall device area increases
Solution Approach 1:
The patent maintains manufacturing simplicity by using consistent fabrication processes for both stacked portions while achieving area reduction through vertical integration. The multi-stack configuration allows sense amplifiers and column selection circuits to be manufactured using similar processes but arranged in different vertical layers, thereby reducing the planar device area without significantly complicating the manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the overall area of the semiconductor storage device and decreases connection resistance, enabling more flexible layout options and improved data retention with fewer refresh operations.
Implementation Method 1
utilizing field effect transistors with oxide semiconductor channel layers for reduced leakage current
Implementation Method 2
The second stacked portion includes a memory cell, a word line connected to the memory cell, a bit line connected to the memory cell and the first peripheral circuit, and at least one of a second peripheral circuit connected to the bit line or a third peripheral circuit connected to the word line
Data Source
AI summary
According to one embodiment, a semiconductor storage device includes a first stacked portion including a first peripheral circuit and a second stacked portion above the first stacked portion. The second stacked portion including a memory cell, a word line connected to the memory cell, a bit line connected to the memory cell and the first peripheral circuit, and at least one of a second peripheral circuit connected to the bit line and a third peripheral circuit connected to the word line. The at least one of the second or third peripheral circuits including a field effect transistor having a channel layer containing an oxide semiconductor.