Semiconductor Storage Device Wiring Layer Integration
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Solution Overview
Problem
Existing semiconductor storage devices require multiple wiring layers to electrically connect memory cells to drive circuits, leading to increased complexity and inefficiency.
Innovation Solution
A semiconductor storage device design that integrates connection wirings for both odd and even numbered cell wiring layers into a single wiring layer, reducing the number of wiring layers needed and optimizing the arrangement of contacts and drive circuits to minimize electric resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate wiring layers are used for odd and even numbered cell wiring layers, then electrical connection is achieved, but the number of wiring layers increases and device complexity increases
Solution Approach 1:
The patent merges the wiring layers for odd and even numbered cell wiring layers into a single common wiring layer. This is achieved by providing a first wiring layer that includes both first wirings (connected to odd numbered cell wiring layers) and second wirings (connected to even numbered cell wiring layers) in the same physical layer, thereby reducing the total number of wiring layers while maintaining reliable electrical connections to all memory cells
2Reliability
If multiple wiring layers are used for connecting memory cells to drive circuits, then electrical connection is achieved, but manufacturing complexity increases
Solution Approach 1:
The patent combines multiple wiring functions into a single wiring layer, reducing the number of fabrication steps required. By integrating both odd and even numbered cell wiring connections in one layer, the manufacturing process requires fewer deposition and patterning steps, thereby reducing manufacturing complexity while ensuring reliable electrical connections
3Productivity
If connection wirings extend in opposite directions from bit line contacts, then wiring efficiency is improved, but wiring layer integration becomes more difficult
Solution Approach 1:
The patent employs asymmetric routing where connection wirings extend in opposite directions from bit line contacts. Specifically, connection wirings from first bit line contacts extend in a first direction while connection wirings from second bit line contacts extend in a second direction opposite to the first. This asymmetric arrangement optimizes wiring efficiency by minimizing overlap and interference, while the systematic nature of the opposite directions simplifies the integration process
Data Source
AI summary
A semiconductor storage device includes first, second, and third wiring layers, each including a plurality of first wirings, fourth and fifth wiring layers, each including a plurality of second wirings, wherein the fourth wiring layer is between the first and second wiring layers and the fifth wiring layer is between the second and third wiring layers, memory cells formed at intersections of the first and second wirings of adjacent wiring layers, first and second contacts electrically connected to a first wiring of the first wiring layer and a first wiring of the second wiring layer, respectively, in the hook-up region, a sixth wiring layer including a first connection wiring electrically connected to the first contact and a second connection wiring electrically connected to the second contact and separated from the first connection wiring, and first and second drive circuits electrically connected to the first and second connection wirings, respectively.