Strain-Inducing Layer Structure for Semiconductor Channel
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Solution Overview
Problem
As semiconductor devices are miniaturized to increase integration density, it becomes challenging to form strain-inducing layers that can effectively apply sufficient strain to the channel region, hindering the improvement of device speed.
Innovation Solution
The semiconductor device incorporates a strain-inducing layer structure with multiple layers, including a first and second strain-inducing layer, where the first strain-inducing layer contacts the gate dielectric layer and the second strain-inducing layer, and optionally a third strain-inducing layer with varying germanium content and doping concentrations, to apply strain to the channel region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor devices are miniaturized to increase integration density, then integration density is improved, but the ability to form effective strain-inducing layers is worsened
Solution Approach 1:
The strain-inducing layer is divided into multiple segments: a first strain-inducing layer in direct contact with the channel region, a second strain-inducing layer above the first layer, and optionally a third strain-inducing layer above the second layer. This segmented structure allows each layer to contribute to strain induction independently, maintaining effective strain application even in miniaturized devices where a single thick layer would be difficult to form.
Solution Approach 2:
Different portions of the strain-inducing structure have different properties: the first strain-inducing layer has high germanium content (50-80 at%) for maximum strain induction at the channel interface, the second layer has moderate germanium content (20-50 at%) for intermediate strain, and the third layer has lower germanium content (0-20 at%) for gradual transition. This local quality variation optimizes strain distribution throughout the vertical profile while enabling formation in miniaturized devices.
2Device complexity
If a single strain-inducing layer is used, then device structure is simple, but sufficient strain cannot be applied to the channel region in miniaturized devices
Solution Approach 1:
The strain-inducing structure transitions from a single-layer horizontal approach to a multi-layer vertical approach. By stacking strain-inducing layers vertically above the channel region, the invention achieves cumulative strain induction in the vertical dimension, thereby applying sufficient strain to the channel region in miniaturized devices without excessive horizontal complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the strain applied to the channel region, improving the speed and performance of miniaturized semiconductor devices by optimizing the thickness and doping concentrations of the strain-inducing layers.
Implementation Method 1
a first strain-inducing layer and a second strain-inducing layer, and the first strain-inducing layer is between a lateral surface of the channel region and the second strain-inducing layer
Data Source
AI summary
Semiconductor devices include a strain-inducing layer capable of applying a strain to a channel region of a transistor included in a miniaturized electronic device, and a method of manufacturing the semiconductor device. The semiconductor device includes a substrate having a channel region; a pair of source/drain regions provided on the substrate and arranged on both sides of the channel region in a first direction; and a gate structure provided on the channel region and comprising a gate electrode pattern extending in a second direction that is different from the first direction, a gate dielectric layer disposed between the channel region and the gate electrode pattern, and a gate spacer covering respective lateral surfaces of the gate electrode pattern and the gate dielectric layer. At least one of the source/drain regions includes a first strain-inducing layer and a second strain-inducing layer. The first strain-inducing layer is disposed between a lateral surface of the channel region and the second strain-inducing layer and contacts at least a portion of the gate dielectric layer.