Semiconductor Package Stress Buffers for 3D Die Corner Cracking

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Three-dimensional semiconductor devices face challenges due to thermo-mechanical stress resulting from coefficient of thermal expansion (CTE) differences among components, leading to cracks and reduced reliability.

Innovation Solution

Incorporation of stress buffers with a lower Young's modulus into the redistribution layer (RDL) to mitigate thermo-mechanical stress, particularly at the corners of semiconductor dies, using flexible materials like polyimide or silicon-based polymers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If three-dimensional semiconductor devices are used to improve integration density and bandwidth, then device performance is improved, but thermo-mechanical stress increases due to CTE differences among stacked chips

Engineering Contradiction:
Improveintegration densityVSAvoidstress resistance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent introduces a stress buffer layer as an intermediary component between the redistribution layer and the semiconductor die. This buffer layer mediates the thermo-mechanical stress generated by CTE differences during thermal cycling, preventing direct stress transmission to the die and underfill layer, thereby resolving the contradiction between maintaining 3D package integrity and accommodating thermal expansion differences

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent changes the mechanical parameter (Young's modulus) of the stress buffer layer to be lower than that of the redistribution layer. This parameter change allows the buffer layer to deform more easily under thermal stress, absorbing expansion differences and preventing crack propagation, thus maintaining reliability while preserving the 3D integration structure

Inventive Principle:
Principle #35Parameter changes

2Reliability

If stress buffers with lower Young's modulus are incorporated into the RDL to mitigate thermo-mechanical stress, then reliability is improved, but device complexity increases

Engineering Contradiction:
Improvecrack preventionVSAvoidpackage structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the redistribution layer structure by introducing a distinct stress buffer layer between the RDL and the semiconductor die. This segmentation allows each layer to perform its specific function: the RDL provides electrical redistribution while the stress buffer layer专门 handles mechanical stress, simplifying the design of each component while improving overall reliability

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The stress buffer layer serves as an intermediary that simplifies the overall package design by absorbing thermal stress that would otherwise require complex stress management mechanisms. This single buffer layer approach is simpler than designing entirely stress-resistant materials for all layers or implementing complex compensation structures

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Reduces thermo-mechanical stress, enhancing the long-term reliability of semiconductor packages by preventing cracks and stress-related damage.

Implementation Method 1

a stress buffer embedded in a top surface of the redistribution layer below a corner of the semiconductor die, the stress buffer having a second Young's modulus that is at least 30% less than the first Young's modulus

Methodology Applied
Scientific EffectElasticity: Elasticity

Data Source

PatentUS20260076205A1Methods of forming a semiconductor package including stress buffers
Publication Date: 2026.03.12 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20260076205A1 patent drawing
  • US20260076205A1 patent drawing
  • US20260076205A1 patent drawing

AI summary

A semiconductor package includes a package substrate; a semiconductor die vertically stacked on the package substrate; a redistribution layer (RDL) including a dielectric material and metal features that electrically connect the semiconductor die to the package substrate, the RDL having a first Young's modulus; a first underfill layer disposed between the RDL and the semiconductor die; and stress buffers embedded in the RDL below corners of the semiconductor die, each stress buffer having a second Youngs modulus that is at least 30% less than the first Youngs modulus.