Semiconductor Stress Layer Fabrication via Dummy Gate Replacement
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Solution Overview
Problem
Conventional semiconductor transistors with stress layers often exhibit undesirable morphology and unstable electrical properties due to the formation of shallow trench isolation (STI) structures, which can hinder the deposition of stress layers and lead to voids and poor electrical contact, resulting in leakage current and degraded performance.
Innovation Solution
The method involves forming dummy gate structures on a semiconductor substrate, creating stress layers between them, and then forming dielectric layers to expose and remove the dummy gates, allowing for the formation of functional gate structures with non-functional gates to ensure complete removal of metal residues and improve electrical isolation, thereby stabilizing the transistor's electrical properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If stress layers are formed in conventional transistors, then carrier mobility is improved, but morphology and electrical stability deteriorate due to STI structures causing voids and poor contact
Solution Approach 1:
The patent applies preliminary action by forming stress layers before creating isolation structures. This sequence allows the stress layers to be deposited continuously across the substrate without interruption from STI structures, ensuring uniform morphology and good electrical contact while maintaining the stress-induced carrier mobility enhancement.
Solution Approach 2:
The patent inverts the conventional fabrication sequence by forming stress layers prior to isolation structures rather than after. This reversal eliminates the problem of STI structures interfering with stress layer deposition, thereby improving both morphology and electrical stability while preserving the beneficial stress effect on carrier mobility.
2Reliability
If dummy gate structures are used to form stress layers, then complete metal residue removal is achieved, but device complexity increases
Solution Approach 1:
The patent uses dummy gate structures as intermediary elements that facilitate complete metal residue removal. These dummy gates serve as placeholders during fabrication and are subsequently removed, ensuring that no metal residues remain in the final device. This approach prioritizes electrical stability over fabrication simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the morphology and electrical stability of stress layers by eliminating residues and preventing leakage current between adjacent gate structures, resulting in improved carrier mobility and reduced leakage current, leading to more reliable semiconductor devices.
Implementation Method 1
Because the lattice constant of SiGe is greater than the lattice constant of Si at room temperature, lattice mismatch can be generated between the epitaxial SiGe and the Si. The SiGe stress layer can thus exert compressive stress to the channel region of the transistor.
Implementation Method 2
At room temperature, the lattice constant of SiC is smaller than the lattice constant of Si, and lattice mismatch can be generated between Si and the epitaxial SiC. The SiC stress layer can thus exert tensile stress to the channel region of the NMOS transistor.
Data Source
AI summary
Semiconductor devices and fabrication methods are provided. A semiconductor substrate is provided having dummy gate structures formed thereon. A stress layer is formed in the semiconductor substrate between adjacent dummy gate structures. A first dielectric layer is formed on the semiconductor substrate, the stress layers, and the sidewall spacers of the dummy gate structures, exposing dummy gate electrode layers. Gate structures are formed in the dielectric layer to replace the dummy gate structures. The gate structures include functional gate structures and at least one non-functional gate structure. The at least one non-functional gate structure is removed to form at least one second opening in the first dielectric layer. At least one third opening is formed in the semiconductor substrate at a bottom of the at least one second opening. A second dielectric layer is formed in the at least one second opening and the at least one third opening.