Semiconductor Structural Member for Warpage Reduction

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Solution Overview

Problem

In semiconductor fabrication, warpage occurs due to mismatch in Coefficient of Thermal Expansion (CTE) between mold compound and silicon dies, and there is a challenge in optimizing the number of dies on a common substrate for space efficiency, with silicon dies potentially shifting during encapsulation.

Innovation Solution

A structural member with die package regions and through-vias is used, which is mated to a temporary carrier substrate with an adhesive, featuring die attach regions and peripheral regions to accommodate and secure silicon dies, reducing warpage and facilitating electrical coupling and stacking.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If silicon dies are mounted onto a common substrate in wafer format for parallel processing, then productivity is improved by processing multiple dies simultaneously, but warpage occurs due to CTE mismatch between mold compound and silicon dies

Engineering Contradiction:
Improveparallel processing capabilityVSAvoidwarpage during encapsulation
Core Design Contradiction:
ProductivityVSStability of the object's composition

Solution Approach 1:

The patent introduces a carrier substrate as an intermediary component between the silicon dies and the molding process. This carrier substrate has a CTE that is intermediate between silicon and mold compound, serving as a buffer to reduce thermal stress and prevent warpage during encapsulation while enabling parallel processing of multiple dies

Inventive Principle:
Principle #24Intermediary (Mediator)

2Length of moving object

If the thickness of silicon dies and substrate is decreased to reduce package size, then miniaturization is achieved, but warpage becomes aggravated due to reduced structural rigidity

Engineering Contradiction:
Improvepackage thicknessVSAvoidwarpage resistance
Core Design Contradiction:
Length of moving objectVSStability of the object's composition

Solution Approach 1:

The patent employs a composite structure consisting of multiple layers including the silicon die, carrier substrate, and mold compound. Each layer has different mechanical and thermal properties, and their combination creates a balanced structure that reduces overall warpage while maintaining thin profile through careful selection and arrangement of materials with complementary properties

Inventive Principle:
Principle #40Composite materials

3Area of stationary object

If more silicon dies are mounted onto the common substrate to maximize space savings, then area efficiency is improved, but die shifting out of designated location occurs during molding

Engineering Contradiction:
Improvesubstrate utilization efficiencyVSAvoiddie positioning accuracy
Core Design Contradiction:
Area of stationary objectVSManufacturing precision

Solution Approach 1:

The patent implements preliminary positioning features on the carrier substrate such as alignment marks, mechanical stops, or adhesive patterns that are prepared in advance. These features ensure that silicon dies are correctly positioned before the molding process begins, preventing die shifting during encapsulation even when multiple dies are densely packed on the substrate

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The structural member effectively reduces warpage during encapsulation, prevents die shifting, and enables efficient packaging and stacking of silicon dies by balancing CTE and providing electrical connectivity through RDL layers.

Implementation Method 1

A structural member which is mated to a first surface of a temporary carrier substrate with an adhesive

Methodology Applied
Scientific EffectAdhesive bonding: Adhesive

Implementation Method 2

The through-vias comprise a conductive material and are electrically coupled to bond pads of the dies

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Implementation Method 3

The structural member can reduce warpage that can occur during curing of the mold compound used in encapsulating the die. The structural member can serve as an interposer which balances CTE of the components of the package

Methodology Applied
Scientific EffectThermal expansion balancing: Thermal Expansion

Data Source

PatentUS9704726B2Packaging structural member
Publication Date: 2017.07.11 UTAC HEADQUARTERS PTE LTD
  • US9704726B2 patent drawing
  • US9704726B2 patent drawing
  • US9704726B2 patent drawing

AI summary

A structural member for use in semiconductor packaging is disclosed. The structural member includes a plurality of packaging regions to facilitate packaging dies in, for example, a wafer format. A packaging region has a die attach region surrounded by a peripheral region. A die is attached to the die attach region. In one aspect, the die attach region has opening through the surfaces of the structural member for accommodating a die. Through-vias disposed are in the peripheral regions. The structural member reduces warpage that can occur during curing of the mold compound used in encapsulating the dies. In another aspect, the die attach region does not have an opening. In such cases, the structural member serves as an interposer between the die and a substrate.