Semiconductor Package With Sub-Chip Leads For I/O Density
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Solution Overview
Problem
Quad Flat No leads (QFN) packages face limitations in input/output (I/O) capacity, as the area beneath the chip is typically not utilized for connections, restricting the package's ability to increase I/O density.
Innovation Solution
The semiconductor package design incorporates second leads positioned partially under the chip with sloped portions, bonding pads outside the chip, and connecting segments to enable I/O connections, along with a filling material between the chip and leads to enhance stability and mechanical hold, allowing the use of leads for I/O operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If leads are arranged only in a perimeter array circumscribing the chip, then the package structure is simple to manufacture, but the I/O capacity is limited
Solution Approach 1:
The patent transitions from a two-dimensional perimeter array arrangement to a three-dimensional configuration by placing leads both around the perimeter and beneath the chip. This dimensional expansion allows additional I/O connections without increasing the package footprint, effectively resolving the contradiction between I/O capacity and structural simplicity.
Solution Approach 2:
The patent nests leads beneath the chip body, utilizing the space under the chip that would otherwise be unused. This nesting approach allows additional leads to be incorporated into the package structure without increasing the external dimensions, thereby increasing I/O capacity while maintaining a compact form factor.
2Quantity of substance
If the area beneath the chip is not utilized for connections, then the chip bonding is simple, but the I/O density is restricted
Solution Approach 1:
The invention utilizes the vertical dimension by placing leads beneath the chip, transforming the bonding process from a purely planar operation to a three-dimensional operation. This allows I/O connections to be established in the z-direction, increasing I/O density without complicating the bonding procedure.
Solution Approach 2:
The patent introduces an intermediary structure (the conductive substrate with recessed areas) that facilitates bonding beneath the chip. This intermediary provides a structured approach to sub-chip connections, making the manufacturing process manageable despite the increased complexity of three-dimensional bonding.
3Stability of the object's composition
If leads are positioned under the chip without filling material, then the manufacturing process is simpler, but mechanical stability is reduced
Solution Approach 1:
The filling material acts as an intermediary substance that bonds the chip to the leads positioned beneath it. This filling material provides mechanical interlocking and adhesion, enhancing the mechanical stability of the package while adding only a single step to the manufacturing process.
Solution Approach 2:
The patent employs composite material structures by combining the chip, leads, and filling material into an integrated assembly. This composite approach creates a mechanically stable structure where each component contributes to the overall strength and stability of the package.
Data Source
AI summary
A semiconductor package includes leads around the periphery of a chip and leads under the chip having connecting segments for increasing I/O capability. A filling material may be used under the chip, which may provide a lead locking function. Various methods of forming the semiconductor package are further provided.