3D Semiconductor Package Substrate with Pre-formed Cavities and Vias
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Solution Overview
Problem
Existing semiconductor package manufacturing processes face challenges in forming 3D structures due to difficulties in manufacturing thru vias, which can lead to electrical and mechanical weaknesses, residual stress-induced warping, and high costs associated with the double-sided build-up process.
Innovation Solution
A method involving a prefabricated substrate with pre-formed vias and cavities, using a photolythic material for encapsulation, and minimizing via drilling by forming interconnect layers and contact terminals without the need for cumbersome drilling and planarization steps, allowing for the creation of a 3D packaged semiconductor device with reduced warping and lower processing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If thru vias are formed within a substrate to provide connections between top and bottom surfaces, then electrical connectivity is achieved, but manufacturing difficulty increases and mechanical weakness is introduced
Solution Approach 1:
The substrate is pre-formed with cavities and vias before the semiconductor device is mounted. This preliminary preparation eliminates the need for complex post-mounting via drilling and planarization, significantly reducing manufacturing difficulty while maintaining electrical connectivity reliability
Solution Approach 2:
The substrate structure is segmented into distinct regions: pre-formed cavities for device mounting, pre-formed vias for electrical connections, and flat regions for interconnect formation. This segmentation allows each feature to be optimized independently, improving both manufacturability and reliability
2Adaptability or versatility
If double sided build up process is used to form 3D structure, then multiple devices can be integrated, but residual stresses cause panel warping
Solution Approach 1:
Cavities and vias are pre-formed in the substrate before device mounting and before adding interconnect layers. This preliminary structuring distributes stresses more evenly throughout the substrate, preventing the cumulative warping that occurs with sequential double-sided build-up processes
Solution Approach 2:
The substrate has locally optimized regions: cavities provide mechanical support and stress relief where devices are mounted, vias provide electrical pathways, and flat regions provide stable bases for interconnect formation. This local optimization prevents global warping while enabling device integration
3Device complexity
If double sided build up process is used, then 3D structure is formed, but processing cost increases due to many processing steps
Solution Approach 1:
The substrate is pre-formed with all necessary cavities, vias, and structural features before device mounting. This eliminates multiple subsequent processing steps including via drilling, planarization, and cavity formation, significantly reducing processing cost while maintaining 3D structure complexity
Solution Approach 2:
Multiple functions are merged into the pre-formed substrate: mechanical support, electrical connectivity pathways, device mounting structures, and stress management features. This consolidation of functions into a single pre-prepared substrate reduces the number of processing steps and lowers overall manufacturing cost
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of robust 3D semiconductor packages with minimized damage and reduced warping, lowering production costs by simplifying the process and eliminating the need for stacked vias, while allowing for the integration of multiple devices in a stacked configuration.
Implementation Method 1
In one embodiment, a photolythic material is used to encapsulate the die.
Data Source
AI summary
A method is used to form a packaged semiconductor device. A semiconductor device, which has an active surface, is placed in an opening of a circuit board. The circuit board has a first major surface and a second major surface having the opening, first vias that extend between the first major surface and the second major surface, first contact pads terminating the vias at the first major surface, and second contact pads terminating the vias at the second major surface. A dielectric layer is applied over the semiconductor device and the second major surface of the circuit board. An interconnect layer is formed over the dielectric layer. The interconnect layer has second vias electrically connected to the second contact pads, third vias that are electrically connected to the active surface of the semiconductor device, an exposed surface, and third contact pads at the exposed surface.