Semiconductor Substrate Grooves for Underfill Resin Control
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Solution Overview
Problem
The existing semiconductor device manufacturing methods face challenges in reducing the size of semiconductor devices while maintaining efficiency, as the three-dimensional mounting structure with Through Silicon Vias (TSV) results in wasted space due to underfill resin outflow and increased thickness, necessitating a reduction in substrate area and device thickness.
Innovation Solution
A semiconductor device manufacturing method involving the formation of grooves in a lattice pattern on the semiconductor substrate to control underfill resin spreading, followed by stacking semiconductor chips, forming sealing resin layers, and grinding the substrate to reduce thickness, allowing for more efficient packaging and size reduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a three-dimensional mounting structure with TSV is used to reduce package size and increase operation frequency, then the operation speed and mounting area efficiency are improved, but the device thickness increases and wasted space is generated due to underfill resin outflow
Solution Approach 1:
The patent introduces groove structures that segment the substrate surface into distinct regions, each capable of holding a stacked body. These grooves prevent underfill resin from flowing between adjacent stacked bodies, thereby eliminating wasted space and reducing the overall device footprint while maintaining the three-dimensional mounting structure's high-frequency performance
Solution Approach 2:
The patent utilizes the vertical dimension by forming grooves with specific depths relative to stacked body heights. By controlling the groove depth to be between 0.01 to 0.5 times the stacked body height, the structure optimizes space utilization in the vertical dimension while preventing horizontal resin overflow, thus reducing wasted space without compromising the stacked body's electrical connectivity
2Area of stationary object
If the surface area of the substrate is reduced to minimize device size, then the package size is reduced, but the spacing between adjacent stacked bodies must be sufficient to accommodate sealing material outflow preventing bodies
Solution Approach 1:
The groove structures act as natural barriers that segment the substrate into discrete mounting regions. This segmentation eliminates the need for additional spacing between stacked bodies, as the grooves themselves prevent resin outflow. Consequently, the substrate surface area is maximized for a given device footprint, allowing more stacked bodies to be arranged in the available space
Solution Approach 2:
The patent merges the functions of spacing provision and resin containment into a single groove structure. The grooves simultaneously serve as physical barriers to prevent underfill resin outflow and as implicit spacers between adjacent stacked bodies, thereby eliminating the need for separate spacing elements and reducing overall device complexity
3Reliability
If sealing material outflow preventing bodies are provided on the metal plate to limit underfill resin spreading, then the resin containment is improved, but the spacing between adjacent stacked bodies increases resulting in wasted space
Solution Approach 1:
The patent extracts the resin containment function from separate outflow preventing bodies and integrates it directly into the substrate structure through grooves. This eliminates the need for additional components, thereby maximizing the usable substrate area while maintaining effective resin containment within each stacked body's designated region
Solution Approach 2:
The groove structures combine multiple functions into a single element: they serve as both the substrate's structural feature and the resin containment barrier. This merging eliminates the need for separate outflow preventing bodies, thereby increasing the usable substrate area without compromising resin containment reliability
Data Source
AI summary
A semiconductor device manufacturing method includes forming grooves in a surface of a semiconductor substrate, stacking a plurality of semiconductor chips in each area of the semiconductor substrate surrounded by the grooves to form stacked bodies, forming a first sealing resin layer that covers spaces between the plurality of semiconductor chips and lateral sides of the stacked bodies, separating the semiconductor substrate to singulate the stacked bodies, mounting the stacked bodies on a wiring substrate, forming a second sealing resin layer that seals the stacked bodies on the wiring substrate, separating the wiring substrate to singulate a portion of the wiring substrate with a single stacked body thereon, and grinding a portion of the semiconductor substrate in a thickness direction from a side of the semiconductor substrate opposite to the stacked bodies, after forming the first sealing resin layer and before singulating the wiring substrate.