Semiconductor Integrated Circuit Substrate Layout Noise Margin
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Solution Overview
Problem
In semiconductor integrated circuits, the area overhead and power consumption increase due to the need for additional substrates and complex substrate potential control, especially in advanced generations like 0.13-μm to 90-nm, where ideal scaling rules for power source and threshold voltage are not followed, leading to noise margin issues and potential faulty operations.
Innovation Solution
A semiconductor integrated circuit design that eliminates the need for an additional substrate of different polarity by using a first substrate of one polarity with two independent substrate potentials and a third substrate of a different polarity, disposed between them, reducing area overhead and allowing for independent substrate potential supply lines, thereby achieving a more compact and efficient layout.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an additional substrate of different polarity is used to ensure noise margin in advanced process generations, then circuit reliability is improved, but area overhead increases
Solution Approach 1:
The patent merges the function of the third substrate (different polarity substrate) with the first and second substrates (same polarity substrates) by eliminating the need for physical isolation structures. The third substrate is positioned adjacent to the first and second substrates without requiring additional isolation substrates, thereby combining multiple substrate functions into a compact arrangement that reduces area overhead while maintaining noise margin through independent substrate potential control.
2Stability of the object's composition
If independent substrate potential control is implemented to maintain noise margin, then circuit stability is improved, but device complexity increases
Solution Approach 1:
The patent segments the substrate potential control by providing independent substrate potential supply lines for the first substrate, second substrate, and third substrate. This segmentation allows each substrate to be controlled independently, maintaining circuit stability through proper noise margin while simplifying the overall control architecture by treating each substrate as an independent control unit rather than requiring complex inter-substrate coordination.
Solution Approach 2:
The third substrate acts as an intermediary element positioned between the first and second substrates. This intermediary substrate provides a physical and electrical buffer that helps maintain noise margin between the first and second substrates while allowing independent potential control, thereby stabilizing the circuit without requiring complex control mechanisms.
3Quantity of substance
If process scaling is performed to reduce transistor size, then transistor density is improved, but noise margin deteriorates
Solution Approach 1:
The patent addresses the noise margin deterioration caused by process scaling by introducing a third substrate dimension adjacent to the first and second substrates. This dimensional addition provides an extra layer of substrate potential control that compensates for the reduced noise margin in scaled transistors, allowing high transistor density to be maintained while recovering noise margin through the additional substrate layer.
Data Source
AI summary
A semiconductor integrated circuit has a first substrate of a first polarity to which a first substrate potential is given, a second substrate of the first polarity to which a second substrate potential different from the first substrate potential is given, and a third substrate of a second polarity different from the first polarity. The first substrate is insulated from a power source or ground to which a source of a MOSFET formed on the substrate is connected. The third substrate is disposed between the first and second substrates in adjacent relation to the first and second substrates. A circuit element is formed on the third substrate.