Power Semiconductor Substrate Segmented Metal Strips Low Inductance
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Solution Overview
Problem
Power semiconductor packages face challenges in achieving low parasitic inductance in commutation circuits, which hinders fast switching of power semiconductors.
Innovation Solution
The integration of a parallel plate waveguide structure into the power semiconductor package design, where the uppermost metal layer is patterned into strips and semiconductor dies are attached evenly across these strips, with DC terminals connected through conductive vias, significantly reduces parasitic inductance by ensuring perpendicular electric and magnetic fields are shielded.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional substrate designs are used, then manufacturing is simpler, but parasitic inductance is high which prevents fast switching
Solution Approach 1:
The uppermost metal layer is segmented into multiple parallel strips instead of a continuous layer. Each strip can be independently connected to semiconductor dies, allowing current to be distributed across multiple parallel paths. This segmentation reduces the loop area and parasitic inductance in the commutation circuit, enabling faster switching speeds while maintaining a relatively simple manufacturing process.
Solution Approach 2:
The patent transitions from a conventional planar substrate design to a multi-layered structure with metal strips extending in the width direction. By adding the dimension of parallel strip configuration and utilizing the width of the substrate effectively, the design creates multiple current paths without increasing the footprint area, thereby reducing parasitic inductance and enabling faster switching.
2Speed
If metal layers are closely spaced to reduce inductance, then parasitic inductance decreases, but electrical insulation becomes more difficult to maintain
Solution Approach 1:
Polymer-based insulating layers are introduced as intermediary materials between the metal layers. These insulating layers provide reliable electrical isolation while allowing the metal layers to be closely spaced for low inductance. The polymer material acts as a mediator that enables both close spacing for performance and adequate insulation for reliability, resolving the contradiction between these two requirements.
Solution Approach 2:
The substrate employs a composite structure combining metal layers with polymer-based insulating materials. This composite approach allows the metal layers to be positioned closely for low parasitic inductance while the polymer insulating layers maintain electrical isolation. The combination of conductive metal and insulating polymer materials enables simultaneous optimization of both inductance and insulation reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design allows for faster switching of power semiconductor dies by minimizing parasitic inductance, enhancing the efficiency and performance of power semiconductor packages, particularly in 3-phase inverters and 3-level circuits.
Implementation Method 1
The first DC terminal is electrically connected to the first intermediary metal layer through a plurality of conductive vias that extend through the third and the second insulating layers
Implementation Method 2
integration of a parallel plate waveguide structure into the power semiconductor package design, where the uppermost metal layer is patterned into strips and semiconductor dies are attached evenly across these strips, with DC terminals connected through conductive vias, significantly reduces parasitic inductance by ensuring perpendicular electric and magnetic fields are shielded
Data Source
AI summary
Power semiconductor packages described herein each include a substrate having two or more metal layers and one or more insulating layers for separating the metal layers. The substrate insulating layers are formed from a polymer material to reduce the CTE mismatch between the substrate metal layers and the substrate insulating layers.