Semiconductor Substrate Through-Wafer Interconnects via Segmented Recesses
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Solution Overview
Problem
Current methods for producing semiconductor substrates with high arrangement density and electrical conductivity are complex, costly, and limited by the need for double etching processes, which reduces mechanical strength and restricts use under high forces and accelerations, and are not compatible with CMOS technology.
Innovation Solution
The method involves forming recesses on the front side of silicon substrates with a minimum depth of 200 μm using dry etching, filling them with doped polysilicon for conductivity, and reducing the substrate thickness from the rear side to expose these recesses, allowing for electrical connections and insulation without the need for double etching, enabling full CMOS processing and improved mechanical strength.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If double etching process is used to form through-wafer interconnections, then electrical conductivity through substrate is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent segments the interconnection formation into two independent stages: (1) forming blind recesses with insulating material and conductive fill from the front side, and (2) forming through-holes from the rear side that connect to the conductive elements. This segmentation allows each etching process to be optimized independently and eliminates the need for complex double etching of continuous through-wafer paths, thereby reducing process complexity while maintaining electrical conductivity.
Solution Approach 2:
The patent performs preliminary action by forming the conductive elements and insulating structures in blind recesses from the front side before creating the through-holes from the rear side. This preliminary formation of conductive pathways allows the subsequent rear-side etching to simply connect to pre-formed structures rather than requiring complex coordinated etching, simplifying the overall process.
2Reliability
If double etching process is used, then through-wafer connections are achieved, but mechanical strength is reduced
Solution Approach 1:
By segmenting the interconnection structure into blind recesses filled with insulating material and separate conductive elements, the patent creates a mechanically robust architecture. The insulating material in the blind recesses provides structural support while the conductive elements maintain electrical pathways, avoiding the mechanical weakness of continuous through-wafer etched paths.
Solution Approach 2:
The patent applies beforehand cushioning by filling the blind recesses with insulating material before forming the through-holes. This insulating material acts as a cushioning structure that maintains mechanical integrity during subsequent processing and under operational stress, preventing the structural degradation that would occur with bare etched through-holes.
3Reliability
If recesses are etched from both front and rear sides, then electrical connections are formed, but manufacturing cost increases
Solution Approach 1:
The patent segments the manufacturing process into independent front-side and rear-side operations that can be performed in separate processing stages. The front-side process forms blind recesses with insulating and conductive layers, while the rear-side process forms through-holes to connect to these structures. This segmentation allows standard CMOS processing techniques to be used for each stage independently, reducing overall manufacturing cost compared to complex double etching.
Solution Approach 2:
The patent applies self-service by forming the conductive elements within the blind recesses during the front-side processing, so that these elements automatically serve as the connection targets for the subsequent rear-side through-holes. This eliminates the need for additional alignment and registration steps that would increase manufacturing cost, as the conductive elements self-align with the through-hole openings.
4Ease of manufacture
If open recesses are left on rear side, then etching is simplified, but vacuum manipulation is adversely affected
Solution Approach 1:
The patent performs preliminary action by forming the conductive elements and insulating structures in blind recesses before creating the through-holes from the rear side. This ensures that when the through-holes are formed, they connect to pre-formed structures rather than leaving open recesses, thereby enabling both simplified etching and proper vacuum sealing for manipulation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for cost-effective production of semiconductor substrates with high arrangement density, good electrical conductivity, and closed surfaces, while maintaining mechanical strength and compatibility with CMOS technology, enabling efficient signal transmission and reduced risk of contamination.
Implementation Method 1
Starting from the front side, at least two recesses are formed with a minimum depth of e.g. 200 μm by etching, e.g. by dry etching
Implementation Method 2
The recesses are then completely filled with an electrically conductive material. The one inwardly arranged recess or also a plurality of inwardly arranged recesses can be filled with e.g. doped polysilicon and can thus form the electrically conductive connection through the semiconductor substrate
Data Source
AI summary
The invention relates to semiconductor substrates and methods for producing such semiconductor substrates. In this connection, it is the object of the invention to provide semiconductor substrates which can be produced more cost-effectively and with which a high arrangement density as well as good electrical conductivity and closed surfaces can be achieved. In accordance with the invention, an electrically conductive connection is guided from its front side through the substrate up to the rear side. The electrically conductive connection is completely surrounded from the outside. The insulator is formed by an opening which is filled with material. The inner wall is provided with a dielectric coating and/or filled with an electrically insulating or conductive material. The electrically conductive connection is formed with a further opening which is filled with an electrically conductive material and is arranged in the interior of the insulator. The openings are formed with step-free inner walls aligned orthogonally to the front side or tapering continuously in the direction of the rear side.