Semiconductor Substrate Signal Line Shielding Layout
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Solution Overview
Problem
Existing semiconductor device manufacturing methods for BGA packages, such as those used in DRAM chips, face challenges in arranging signal lines between power and ground lines effectively, leading to limited data transfer rates due to constraints in pad layout and line arrangement.
Innovation Solution
A method for manufacturing semiconductor devices with a substrate featuring predetermined layouts of signal, power, and ground lines, where signal lines are arranged between power and ground lines within distinct regions, allowing for optimal connection of pads and terminals to enhance signal integrity and data transfer rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If signal lines are arranged between power and ground lines to improve signal integrity and data transfer rates, then signal shielding is improved, but pad layout constraints prevent effective arrangement of all signal lines
Solution Approach 1:
The patent transitions from a two-dimensional pad layout on the chip surface to a three-dimensional arrangement by extending signal lines onto the substrate beneath the chip. This allows signal lines to be arranged between power and ground lines on the substrate level, achieving effective shielding without being constrained by the limited pad layout on the chip surface.
Solution Approach 2:
The substrate serves as an intermediary layer between the chip pads and the external terminals. By routing signal lines through the substrate, the patent enables signal lines to be positioned between power and ground lines on the substrate level, achieving shielding without requiring direct pad arrangement on the chip surface.
2Productivity
If more signal lines are arranged between power and ground lines to increase data transfer rates, then signal shielding and data transfer performance are improved, but the number of required pads increases beyond available pad capacity
Solution Approach 1:
The patent moves the signal line arrangement from the chip pad level to the substrate level, effectively creating additional routing dimensions. This allows multiple signal lines to be arranged between power and ground lines on the substrate without requiring additional pads on the chip surface.
Solution Approach 2:
The patent separates the signal routing function from the pad connection function. The pads on the chip surface maintain their limited数量 for mechanical connection, while the signal lines are segmented and routed independently on the substrate level between power and ground lines, enabling enhanced shielding without increasing pad count.
3Ease of manufacture
If existing pad layouts are used to maintain compatibility with JEDEC standards, then manufacturing compatibility is improved, but signal line arrangement between power and ground lines is not achieved
Solution Approach 1:
The patent maintains the existing two-dimensional pad layout on the chip surface for JEDEC compatibility, while adding a third dimension by routing signal lines on the substrate beneath the chip. This enables signal lines to be arranged between power and ground lines on the substrate level, achieving effective shielding without changing the pad layout.
Solution Approach 2:
The patent separates the pad layout function (maintained for compatibility) from the signal routing function (optimized for shielding). The pads remain in their standard positions for manufacturing compatibility, while the signal lines are segmented and routed independently on the substrate to achieve arrangement between power and ground lines.
Data Source
AI summary
Disclosed is a method for manufacturing a method for manufacturing a semiconductor device which comprises a substrate, a semiconductor chip and a plurality of terminals. The method comprises preparing the substrate comprising an insulator which is formed with a plurality of signal lines, a plurality of power lines related to the plurality of signal lines and a plurality of ground lines related to the plurality of signal lines on the insulator in accordance with a predetermined layout. Each of the plurality of line groups comprises one of the power lines, one of the ground lines and one of the signal lines arranged between the one of the power lines and the one of the ground lines. Each of the plurality of line groups shares any one of the power line and the ground line with a neighboring line group of the plurality of line groups.