Semiconductor Substrate Trench Stress Management for Bow Height Control
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Solution Overview
Problem
The increasing size of wafers and shrinking device size in semiconductor technology lead to varying stress concentrations in array and periphery regions, causing high bow height issues that affect film deposition uniformity and critical dimension accuracy.
Innovation Solution
A semiconductor substrate with large-area and deep trenches, along with tensile or compressive stress layers in the trenches, is used to manage bow height, where the trenches' depth-to-thickness ratio and area ratio are optimized between 0.001 and 0.008 and 5% to 90% respectively, and stress layer thickness is between 20 Å and 1.5 μm.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If wafer size increases to form more chips per wafer, then productivity increases, but stress concentration varies between array and periphery regions causing bow height issues
Solution Approach 1:
The wafer is segmented into array regions and periphery regions with different trench configurations. Array regions have trenches with specific depth-to-thickness ratios (0.003-0.006) while periphery regions have different configurations, allowing stress management in each zone to maintain overall flatness while maximizing chip density
Solution Approach 2:
Different regions of the wafer are given different local properties through varying trench depths, trench areas (5%-90% of chip area), and stress layer configurations. This local customization of stress compensation allows the entire wafer to maintain uniform flatness despite size increases
2Reliability
If positive bow height is too high, then wafer may not be adsorbed causing process failure, but if negative bow height is too high, then critical dimension errors occur and film deposits on wafer back
Solution Approach 1:
The invention changes physical parameters including trench depth (controlling depth-to-thickness ratio between 0.001-0.008), trench area ratios (5%-90%), and stress layer thickness (20 Å - 1.5 μm) to precisely control bow height within the optimal range, preventing both adsorption failure and critical dimension errors
3Manufacturing precision
If trenches with stress layers are added to reduce bow height, then manufacturing precision improves, but device complexity increases
Solution Approach 1:
Rather than adding complex structures, the invention achieves bow height control by optimizing parameters of existing trench structures - adjusting depth ratios, area distributions, and stress layer thicknesses. This parameter-based approach maintains structural simplicity while achieving precise flatness control
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces bow height during semiconductor processes, ensuring uniform film deposition and accurate critical dimensions by mitigating stress-related issues in both array and periphery regions.
Implementation Method 1
the bow height problem caused by differences in (deposited) materials and layout of the semiconductor device during processes can be released
Implementation Method 2
a tensile stress layer formed on a bottom of the trenches
Implementation Method 3
a compressive stress layer formed on a bottom of the trenches
Data Source
AI summary
A semiconductor substrate and a semiconductor device are provided in which the substrate includes a plurality of chips. Each of the chips includes at least one array region and at least one periphery region. The semiconductor substrate has a plurality of trenches disposed in the array region and/or the periphery region, wherein a ratio of the depth of the trenches to the thickness of the semiconductor substrate is between 0.001 and 0.008, and the area of all the trenches is between 5% and 90% based on the total area of the semiconductor substrate.