Semiconductor Super-Junction Device Impurity Diffusion Control
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Solution Overview
Problem
High breakdown voltage semiconductor devices face a trade-off between low ON resistance and high avalanche resistance, making it difficult to simultaneously reduce ON resistance and maintain avalanche resistance due to the compensation effects of impurity diffusion during heat treatment.
Innovation Solution
The semiconductor device employs a super-junction structure with alternately arranged n-type and p-type pillar layers, where the p-type diffusion layer is selectively formed with higher impurity concentration and positioned between the n-type and p-type pillar layers, and the n-type source layer is strategically placed at the second end portion of the p-type pillar layer to reduce ON resistance while maintaining avalanche resistance by avoiding electric field concentration and parasitic bipolar transistor turn-on.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If heat treatment is applied to control impurity diffusion, then manufacturing precision improves, but parasitic bipolar transistor turn-on occurs reducing avalanche resistance
Solution Approach 1:
The p-type pillar layers are formed with controlled impurity concentration before the final heat treatment step. The n-type source layer is then formed with high impurity concentration in a selective region. Subsequent heat treatment diffuses impurities in a controlled manner to achieve the desired profile without causing parasitic bipolar transistor turn-on, because the structure is pre-configured to prevent such effects
Solution Approach 2:
The p-type pillar layers act as an intermediary structure between the drift layer and the n-type source layer. They control the impurity diffusion process during heat treatment by providing a buffer that prevents excessive diffusion from the source layer into the drift layer, thereby maintaining avalanche resistance while achieving low ON resistance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces ON resistance while maintaining high avalanche resistance by controlling impurity diffusion and suppressing parasitic bipolar transistor turn-on, thereby stabilizing the device's performance across varying manufacturing processes.
Implementation Method 1
the compensation effects of impurity diffusion during heat treatment
Implementation Method 2
compensation effects of impurity diffusion during heat treatment
Data Source
AI summary
A semiconductor device includes a semiconductor body, first and second electrodes, and a control electrode. The semiconductor body includes first to fourth semiconductor layers. The first electrode is provided on a front surface of the semiconductor body. The second electrode is provided on a back surface of the semiconductor body. The control electrode is provided between the semiconductor body and the first electrode. The second semiconductor layer is positioned between a portion and other portion of the first semiconductor layer in a first direction directed along the front surface. The third semiconductor layer contacts the portion of first semiconductor layer and the second semiconductor layer. The third semiconductor layer includes a first end portion positioned in the portion of the first semiconductor layer and a second end portion positioned in the second semiconductor layer. The fourth semiconductor layer is selectively provided in the second end portion.