Semiconductor Super Junction Insulating Region Chip Size
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Solution Overview
Problem
Conventional semiconductor devices with super junction structures face challenges in reducing chip size while maintaining breakdown voltage, leading to increased manufacturing costs and on-resistance due to the need for larger terminal regions and complex manufacturing processes.
Innovation Solution
A semiconductor device with a super junction structure that incorporates an insulating region surrounding the element region, eliminating the need for a terminal region by ensuring the depletion layer spreads vertically without curvature, thereby reducing chip size and on-resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If p type semiconductor layers and n type semiconductor layers are alternately arranged in the terminal region to secure breakdown voltage, then breakdown voltage is improved, but chip area increases
Solution Approach 1:
The invention divides the terminal region into multiple cell regions, each containing a portion of the alternating p type and n type semiconductor layers. This segmentation allows the depletion layers from adjacent cells to interact and spread vertically, achieving the required breakdown voltage with reduced horizontal spread and smaller overall chip area.
Solution Approach 2:
The invention nests multiple cell regions within the terminal region, where each cell contains a simplified structure of alternating semiconductor layers. These nested cells work together to achieve the cumulative breakdown voltage requirement without requiring a large terminal region, thus reducing chip area while maintaining reliability.
2Reliability
If a terminal region is provided around the element region to maintain breakdown voltage, then breakdown voltage is improved, but manufacturing cost increases
Solution Approach 1:
By segmenting the terminal region into multiple cell regions with alternating semiconductor layers, the invention reduces the overall terminal region size. This reduction directly decreases manufacturing complexity and cost while maintaining the necessary breakdown voltage through the coordinated operation of segmented depletion layers.
3Stress or pressure
If the depletion layer spreads in curved surface shape at the end portion, then the internal electric field concentrates, but breakdown voltage decreases
Solution Approach 1:
The invention segments the terminal region into multiple cells with alternating semiconductor layers, which transforms the curved surface depletion layer into a series of interacting planar depletion layers. This segmentation prevents excessive electric field concentration at curved surfaces while maintaining adequate breakdown voltage through the combined effect of multiple segmented depletion regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces chip size by approximately 30% and decreases on-resistance by eliminating the need for additional semiconductor regions and guard rings, while maintaining sufficient breakdown voltage, thus lowering manufacturing costs.
Implementation Method 1
in a depletion layer formed in a junction surface between an n type impurity semiconductor layer and a p type impurity semiconductor layer, an internal electric field in the direction from the n type to the p type is formed
Implementation Method 2
When a reverse voltage is applied, high breakdown voltage can be achieved in the pn junctions by selecting dopant concentrations and widths of the p type semiconductor layers and n type semiconductor layers to be desired values
Data Source
AI summary
Provided is a semiconductor device in which an insulating region surrounding an element region is provided in an end portion of a semiconductor region with a super junction structure. Since a depletion layer in the element region ends in the insulating region, the end portion of the element region is not formed in a curved surface shape. In other words, the depletion layer has no curved surface in which internal electric fields are concentrated. For this reason, there is no need to take a measure to cause the depletion layer to spread in a horizontal direction by proving a terminal region. Since the terminal region is unnecessary, a chip size can be reduced. Alternatively, an area of the element region can be expanded.