Semiconductor Switching Device with Varying Gate-Drain Capacitance
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Solution Overview
Problem
Semiconductor switching devices with large chip areas experience inhomogeneous switching signal distribution, leading to concurrent operation failures due to uneven current distribution across the chip area, where cells near the gate signal emitters carry excessive current and switch prematurely, while inner cells are not switched simultaneously.
Innovation Solution
The semiconductor device incorporates a layout with different gate-drain capacitance in various switchable regions by varying the specific coverage ratio of the gate electrode structure, allowing for a gradual and synchronized switching of cells across the active area by adjusting the cell layout and gate metallization, ensuring even signal distribution and reducing local overstress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If switchable cells are arranged in a uniform layout across the chip area, then manufacturing is simple, but cells near gate signal emitters receive switching signals earlier and carry excessive current while inner cells switch later, causing inhomogeneous switching
Solution Approach 1:
The patent applies local quality by varying the gate-drain capacitance in different regions of the chip. Specifically, switchable cells near the gate signal emitters (outer rim) are designed with different gate-drain capacitance values compared to cells in the inner region. This local differentiation compensates for the timing differences in signal reception, allowing cells at different positions to switch simultaneously despite the spatial distribution of gate signal emitters.
2Ease of manufacture
If gate signal emitters are placed at the outer rim, then signal distribution is simplified, but cells near the emitters carry full load current and may exceed rated current, causing local overstress
Solution Approach 1:
The patent employs parameter changes by adjusting the gate-drain capacitance parameter of switchable cells based on their spatial location. Cells closer to the gate signal emitters are assigned different capacitance values compared to those farther away. This parameter variation ensures that the switching timing is compensated for the different signal propagation distances, preventing premature switching and excessive current concentration in cells near the emitters, thereby eliminating local overstress while maintaining the simplified outer-rim emitter configuration.
3Reliability
If switchable cells have uniform gate-drain capacitance, then device structure is simplified, but simultaneous operation of all cells cannot be ensured due to varying signal propagation times across the chip area
Solution Approach 1:
The patent implements local quality by creating spatially varying gate-drain capacitance characteristics across the chip area. Different regions are assigned different capacitance values to compensate for the varying distances from gate signal emitters. This ensures that despite the simplified uniform cell structure and outer-rim emitter placement, all cells can operate concurrently with proper timing synchronization.
Data Source
AI summary
A method for manufacturing a semiconductor device includes providing a semiconductor substrate having an outer rim, an active area, and an edge termination region arranged between the active area and the outer rim, and forming a plurality of switchable cells in the active area. Each of the switchable cells includes a body region, a gate electrode structure, and a source region. The active area defined by the switchable cells includes at least a first switchable region having a specific gate-drain capacitance which is different to a specific gate-drain capacitance of a second switchable region. The method further includes forming a source metallization in ohmic contact with the source regions of the switchable cells, and forming a gate metallization in ohmic contact with the gate electrode structures of the switchable cells.