Semiconductor Device Impurity Profile for Switching Speed
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Solution Overview
Problem
Current semiconductor devices, particularly power converters, face challenges in improving the characteristics of Free Wheeling Diodes (FWDs) such as switching time, ON voltage, and leakage current, which are essential for efficient operation.
Innovation Solution
The semiconductor device design includes specific layer configurations with varying impurity concentrations and contacts between electrodes, optimizing the impurity concentration profile to reduce electron and hole injection, thereby improving switching speed and reducing leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the impurity concentration in the semiconductor layers is increased to improve conductivity, then the ON voltage decreases, but the leakage current increases
Solution Approach 1:
The patent applies different impurity concentration levels to different semiconductor layers: the first and third semiconductor layers have higher impurity concentrations (1×10^18 to 1×10^20 atoms/cm³) to reduce ON voltage, while the second semiconductor layer has lower impurity concentration (1×10^16 to 1×10^18 atoms/cm³) to suppress leakage current. This local differentiation of material properties resolves the contradiction between low ON voltage and low leakage current.
2Device complexity
If the semiconductor layer structure is simplified to reduce device complexity, then manufacturing becomes easier, but switching speed deteriorates
Solution Approach 1:
The patent segments the semiconductor structure into four distinct layers with specific impurity concentration profiles: first semiconductor layer (high impurity), second semiconductor layer (low impurity), third semiconductor layer (high impurity), and fourth semiconductor layer (high impurity). This segmentation creates optimal conditions for fast switching by controlling carrier injection and recombination in each layer, achieving switching speed improvement without excessive complexity.
Solution Approach 2:
The patent systematically changes the impurity concentration parameter across different layers to optimize switching characteristics. The first and third layers use high impurity concentrations (1×10^18 to 1×10^20 atoms/cm³) for fast carrier injection, while the second layer uses low impurity concentration (1×10^16 to 1×10^18 atoms/cm³) for rapid carrier removal, enabling fast switching speed.
3Loss of time
If the impurity concentration profile is optimized to reduce carrier injection, then switching time decreases, but the ON voltage increases
Solution Approach 1:
The patent applies different impurity concentration levels to different semiconductor layers: the first and third semiconductor layers have higher impurity concentrations (1×10^18 to 1×10^20 atoms/cm³) to reduce ON voltage, while the second semiconductor layer has lower impurity concentration (1×10^16 to 1×10^18 atoms/cm³) to suppress leakage current. This local differentiation of material properties resolves the contradiction between low ON voltage and low leakage current.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design results in faster switching times, lower switching losses, and reduced leakage current, enhancing the overall performance and reliability of the semiconductor device, especially at high temperatures.
Implementation Method 1
a first semiconductor layer of a first conductivity type, the first semiconductor layer being provided between the first electrode and the second electrode... a second semiconductor layer of a first conductivity type... the second semiconductor layer having an effective impurity concentration lower than an effective impurity concentration in the first semiconductor layer... a third semiconductor layer of a first conductivity type... the third semiconductor layer having an effective impurity concentration lower than an effective impurity concentration in the second semiconductor layer
Data Source
AI summary
According one embodiment, a semiconductor device includes: a first electrode; a second electrode; a first semiconductor layer provided between the first electrode and the second electrode and being in contact with the first electrode; a second semiconductor layer including a first part and a second part, and the second part being contact with the first electrode, and the second semiconductor layer having an effective impurity concentration lower than an effective impurity concentration in the first semiconductor layer; a third semiconductor layer provided between the second semiconductor layer and the second electrode, and having an effective impurity concentration lower than an effective impurity concentration in the second semiconductor layer; and a fourth semiconductor layer provided between the third semiconductor layer and the second electrode, and being in contact with the second electrode.